Logical phy #75
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Logical phy #75
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…o v1.1.2 (#44) Co-authored-by: renovate[bot] <29139614+renovate[bot]@users.noreply.github.com>
Co-authored-by: renovate[bot] <29139614+renovate[bot]@users.noreply.github.com>
Co-authored-by: renovate[bot] <29139614+renovate[bot]@users.noreply.github.com>
Co-authored-by: renovate[bot] <29139614+renovate[bot]@users.noreply.github.com>
Co-authored-by: renovate[bot] <29139614+renovate[bot]@users.noreply.github.com>
The scalafmt sometimes creates weird formatting in the code. Since the chipyard framework does not check it, it can be removed.
| @@ -4,6 +4,11 @@ package interfaces | |||
| import chisel3._ | |||
| import chisel3.util._ | |||
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| class FifoParams extends Bundle { | |||
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is this Params or bundle?
What is this used for? can you not make clk and reset as signals in the main bundle?
src/main/scala/interfaces/Afe.scala
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| /** Data to transmit on the sideband. | ||
| * | ||
| * Output from the async FIFO. | ||
| */ | ||
| val txData = Decoupled(Bits(afeParams.sbSerializerRatio.W)) | ||
| val txData = Input(UInt(afeParams.sbWidth.W)) |
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Why is tx an input? Same with rx being an output? I know you might have flipped it but makes readability hard.
| val out = Decoupled(UInt(params.outWidth.W)) | ||
| } | ||
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| class DataWidthCoupler(params: DataWidthCouplerParams) extends Module { |
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Can you add some comment on top of this class on what this does and where it is used?
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| class Lanes( | ||
| afeParams: AfeParams, | ||
| queueParams: AsyncQueueParams, |
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are you taking the default queueParams? if yes, make sure the queue has sync>=3.
vikramjain236
approved these changes
Apr 22, 2024
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