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Merge stefan #83

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a514eb0
Pushing mbafe source code and module testbench. Waiting to sync with …
Stefanshi2019 May 8, 2024
ddb3568
Integrated mbAfe
Stefanshi2019 May 8, 2024
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258 changes: 258 additions & 0 deletions PhyTest/tb_PhyTest.sv
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`timescale 1ns/100ps
// Testbench for PhyTest
module tb_PhyTest;
// Default clock

reg clock;
reg reset;
reg io_tx_user_txData_ready;
reg io_tx_user_rxData_valid;
reg [7:0] io_tx_user_rxData_bits_0;
reg [7:0] io_tx_user_rxData_bits_1;
reg [7:0] io_tx_user_rxData_bits_2;
reg [7:0] io_tx_user_rxData_bits_3;
reg [7:0] io_tx_user_rxData_bits_4;
reg [7:0] io_tx_user_rxData_bits_5;
reg [7:0] io_tx_user_rxData_bits_6;
reg [7:0] io_tx_user_rxData_bits_7;
reg [7:0] io_tx_user_rxData_bits_8;
reg [7:0] io_tx_user_rxData_bits_9;
reg [7:0] io_tx_user_rxData_bits_10;
reg [7:0] io_tx_user_rxData_bits_11;
reg [7:0] io_tx_user_rxData_bits_12;
reg [7:0] io_tx_user_rxData_bits_13;
reg [7:0] io_tx_user_rxData_bits_14;
reg [7:0] io_tx_user_rxData_bits_15;
reg io_rx_user_txData_ready;
reg io_rx_user_rxData_valid;
reg [7:0] io_rx_user_rxData_bits_0;
reg [7:0] io_rx_user_rxData_bits_1;
reg [7:0] io_rx_user_rxData_bits_2;
reg [7:0] io_rx_user_rxData_bits_3;
reg [7:0] io_rx_user_rxData_bits_4;
reg [7:0] io_rx_user_rxData_bits_5;
reg [7:0] io_rx_user_rxData_bits_6;
reg [7:0] io_rx_user_rxData_bits_7;
reg [7:0] io_rx_user_rxData_bits_8;
reg [7:0] io_rx_user_rxData_bits_9;
reg [7:0] io_rx_user_rxData_bits_10;
reg [7:0] io_rx_user_rxData_bits_11;
reg [7:0] io_rx_user_rxData_bits_12;
reg [7:0] io_rx_user_rxData_bits_13;
reg [7:0] io_rx_user_rxData_bits_14;
reg [7:0] io_rx_user_rxData_bits_15;
reg io_clkp;
reg io_clkn;

wire io_tx_user_txData_valid;
wire [7:0] io_tx_user_txData_bits_0;
wire [7:0] io_tx_user_txData_bits_1;
wire [7:0] io_tx_user_txData_bits_2;
wire [7:0] io_tx_user_txData_bits_3;
wire [7:0] io_tx_user_txData_bits_4;
wire [7:0] io_tx_user_txData_bits_5;
wire [7:0] io_tx_user_txData_bits_6;
wire [7:0] io_tx_user_txData_bits_7;
wire [7:0] io_tx_user_txData_bits_8;
wire [7:0] io_tx_user_txData_bits_9;
wire [7:0] io_tx_user_txData_bits_10;
wire [7:0] io_tx_user_txData_bits_11;
wire [7:0] io_tx_user_txData_bits_12;
wire [7:0] io_tx_user_txData_bits_13;
wire [7:0] io_tx_user_txData_bits_14;
wire [7:0] io_tx_user_txData_bits_15;
wire io_tx_user_rxData_ready;
wire io_rx_user_txData_valid;
wire [7:0] io_rx_user_txData_bits_0;
wire [7:0] io_rx_user_txData_bits_1;
wire [7:0] io_rx_user_txData_bits_2;
wire [7:0] io_rx_user_txData_bits_3;
wire [7:0] io_rx_user_txData_bits_4;
wire [7:0] io_rx_user_txData_bits_5;
wire [7:0] io_rx_user_txData_bits_6;
wire [7:0] io_rx_user_txData_bits_7;
wire [7:0] io_rx_user_txData_bits_8;
wire [7:0] io_rx_user_txData_bits_9;
wire [7:0] io_rx_user_txData_bits_10;
wire [7:0] io_rx_user_txData_bits_11;
wire [7:0] io_rx_user_txData_bits_12;
wire [7:0] io_rx_user_txData_bits_13;
wire [7:0] io_rx_user_txData_bits_14;
wire [7:0] io_rx_user_txData_bits_15;
wire io_rx_user_rxData_ready;
wire io_clkn_out;
always #2.5 io_clkp = ~io_clkp;
always #2.5 io_clkn = ~io_clkn;
always #5 clock = ~clock;

// Signal initializations
initial begin
clock = 0;
reset = 0;
io_tx_user_txData_ready = 0;
io_tx_user_rxData_valid = 0;
io_tx_user_rxData_bits_0 = 0;
io_tx_user_rxData_bits_1 = 0;
io_tx_user_rxData_bits_2 = 0;
io_tx_user_rxData_bits_3 = 0;
io_tx_user_rxData_bits_4 = 0;
io_tx_user_rxData_bits_5 = 0;
io_tx_user_rxData_bits_6 = 0;
io_tx_user_rxData_bits_7 = 0;
io_tx_user_rxData_bits_8 = 0;
io_tx_user_rxData_bits_9 = 0;
io_tx_user_rxData_bits_10 = 0;
io_tx_user_rxData_bits_11 = 0;
io_tx_user_rxData_bits_12 = 0;
io_tx_user_rxData_bits_13 = 0;
io_tx_user_rxData_bits_14 = 0;
io_tx_user_rxData_bits_15 = 0;
io_rx_user_txData_ready = 0;
io_rx_user_rxData_valid = 0;
io_rx_user_rxData_bits_0 = 0;
io_rx_user_rxData_bits_1 = 0;
io_rx_user_rxData_bits_2 = 0;
io_rx_user_rxData_bits_3 = 0;
io_rx_user_rxData_bits_4 = 0;
io_rx_user_rxData_bits_5 = 0;
io_rx_user_rxData_bits_6 = 0;
io_rx_user_rxData_bits_7 = 0;
io_rx_user_rxData_bits_8 = 0;
io_rx_user_rxData_bits_9 = 0;
io_rx_user_rxData_bits_10 = 0;
io_rx_user_rxData_bits_11 = 0;
io_rx_user_rxData_bits_12 = 0;
io_rx_user_rxData_bits_13 = 0;
io_rx_user_rxData_bits_14 = 0;
io_rx_user_rxData_bits_15 = 0;
io_clkp = 0;
io_clkn = 1;
end

PhyTest uut (
.clock(clock),
.reset(reset),
.io_tx_user_txData_ready(io_tx_user_txData_ready),
.io_tx_user_rxData_valid(io_tx_user_rxData_valid),
.io_tx_user_rxData_bits_0(io_tx_user_rxData_bits_0),
.io_tx_user_rxData_bits_1(io_tx_user_rxData_bits_1),
.io_tx_user_rxData_bits_2(io_tx_user_rxData_bits_2),
.io_tx_user_rxData_bits_3(io_tx_user_rxData_bits_3),
.io_tx_user_rxData_bits_4(io_tx_user_rxData_bits_4),
.io_tx_user_rxData_bits_5(io_tx_user_rxData_bits_5),
.io_tx_user_rxData_bits_6(io_tx_user_rxData_bits_6),
.io_tx_user_rxData_bits_7(io_tx_user_rxData_bits_7),
.io_tx_user_rxData_bits_8(io_tx_user_rxData_bits_8),
.io_tx_user_rxData_bits_9(io_tx_user_rxData_bits_9),
.io_tx_user_rxData_bits_10(io_tx_user_rxData_bits_10),
.io_tx_user_rxData_bits_11(io_tx_user_rxData_bits_11),
.io_tx_user_rxData_bits_12(io_tx_user_rxData_bits_12),
.io_tx_user_rxData_bits_13(io_tx_user_rxData_bits_13),
.io_tx_user_rxData_bits_14(io_tx_user_rxData_bits_14),
.io_tx_user_rxData_bits_15(io_tx_user_rxData_bits_15),
.io_rx_user_txData_ready(io_rx_user_txData_ready),
.io_rx_user_rxData_valid(io_rx_user_rxData_valid),
.io_rx_user_rxData_bits_0(io_rx_user_rxData_bits_0),
.io_rx_user_rxData_bits_1(io_rx_user_rxData_bits_1),
.io_rx_user_rxData_bits_2(io_rx_user_rxData_bits_2),
.io_rx_user_rxData_bits_3(io_rx_user_rxData_bits_3),
.io_rx_user_rxData_bits_4(io_rx_user_rxData_bits_4),
.io_rx_user_rxData_bits_5(io_rx_user_rxData_bits_5),
.io_rx_user_rxData_bits_6(io_rx_user_rxData_bits_6),
.io_rx_user_rxData_bits_7(io_rx_user_rxData_bits_7),
.io_rx_user_rxData_bits_8(io_rx_user_rxData_bits_8),
.io_rx_user_rxData_bits_9(io_rx_user_rxData_bits_9),
.io_rx_user_rxData_bits_10(io_rx_user_rxData_bits_10),
.io_rx_user_rxData_bits_11(io_rx_user_rxData_bits_11),
.io_rx_user_rxData_bits_12(io_rx_user_rxData_bits_12),
.io_rx_user_rxData_bits_13(io_rx_user_rxData_bits_13),
.io_rx_user_rxData_bits_14(io_rx_user_rxData_bits_14),
.io_rx_user_rxData_bits_15(io_rx_user_rxData_bits_15),
.io_clkp(io_clkp),
.io_clkn(io_clkn),
.io_tx_user_txData_valid(io_tx_user_txData_valid),
.io_tx_user_txData_bits_0(io_tx_user_txData_bits_0),
.io_tx_user_txData_bits_1(io_tx_user_txData_bits_1),
.io_tx_user_txData_bits_2(io_tx_user_txData_bits_2),
.io_tx_user_txData_bits_3(io_tx_user_txData_bits_3),
.io_tx_user_txData_bits_4(io_tx_user_txData_bits_4),
.io_tx_user_txData_bits_5(io_tx_user_txData_bits_5),
.io_tx_user_txData_bits_6(io_tx_user_txData_bits_6),
.io_tx_user_txData_bits_7(io_tx_user_txData_bits_7),
.io_tx_user_txData_bits_8(io_tx_user_txData_bits_8),
.io_tx_user_txData_bits_9(io_tx_user_txData_bits_9),
.io_tx_user_txData_bits_10(io_tx_user_txData_bits_10),
.io_tx_user_txData_bits_11(io_tx_user_txData_bits_11),
.io_tx_user_txData_bits_12(io_tx_user_txData_bits_12),
.io_tx_user_txData_bits_13(io_tx_user_txData_bits_13),
.io_tx_user_txData_bits_14(io_tx_user_txData_bits_14),
.io_tx_user_txData_bits_15(io_tx_user_txData_bits_15),
.io_tx_user_rxData_ready(io_tx_user_rxData_ready),
.io_rx_user_txData_valid(io_rx_user_txData_valid),
.io_rx_user_txData_bits_0(io_rx_user_txData_bits_0),
.io_rx_user_txData_bits_1(io_rx_user_txData_bits_1),
.io_rx_user_txData_bits_2(io_rx_user_txData_bits_2),
.io_rx_user_txData_bits_3(io_rx_user_txData_bits_3),
.io_rx_user_txData_bits_4(io_rx_user_txData_bits_4),
.io_rx_user_txData_bits_5(io_rx_user_txData_bits_5),
.io_rx_user_txData_bits_6(io_rx_user_txData_bits_6),
.io_rx_user_txData_bits_7(io_rx_user_txData_bits_7),
.io_rx_user_txData_bits_8(io_rx_user_txData_bits_8),
.io_rx_user_txData_bits_9(io_rx_user_txData_bits_9),
.io_rx_user_txData_bits_10(io_rx_user_txData_bits_10),
.io_rx_user_txData_bits_11(io_rx_user_txData_bits_11),
.io_rx_user_txData_bits_12(io_rx_user_txData_bits_12),
.io_rx_user_txData_bits_13(io_rx_user_txData_bits_13),
.io_rx_user_txData_bits_14(io_rx_user_txData_bits_14),
.io_rx_user_txData_bits_15(io_rx_user_txData_bits_15),
.io_rx_user_rxData_ready(io_rx_user_rxData_ready),
.io_clkn_out(io_clkn_out)
);

// Dump waveforms
initial begin
$dumpfile("PhyTest.vcd");
$dumpvars(0, tb_PhyTest);
end

// Reset handling
initial begin
reset = 1'b1;
@(negedge clock);
repeat(9) @(negedge clock);
reset = 1'b0;

for(int i = 0; i < 4; i++) begin
@(negedge clock);
io_tx_user_rxData_valid = 'b1;
io_rx_user_txData_ready = 'b1;
io_tx_user_rxData_bits_0 = i+1;
io_tx_user_rxData_bits_1 = i+1;
io_tx_user_rxData_bits_2 = i+1;
io_tx_user_rxData_bits_3 = i+1;
io_tx_user_rxData_bits_4 = i+1;
io_tx_user_rxData_bits_5 = i+1;
io_tx_user_rxData_bits_6 = i+1;
io_tx_user_rxData_bits_7 = i+1;
io_tx_user_rxData_bits_8 = i+1;
io_tx_user_rxData_bits_9 = i+1;
io_tx_user_rxData_bits_10 = i+1;
io_tx_user_rxData_bits_11 = i+1;
io_tx_user_rxData_bits_12 = i+1;
io_tx_user_rxData_bits_13 = i+1;
io_tx_user_rxData_bits_14 = i+1;
io_tx_user_rxData_bits_15 = i+1;
end
@(negedge clock)
io_tx_user_rxData_valid = 'b0;

repeat(20) @(negedge clock);
repeat(20) @(negedge clock);
$display("Simulation completed");
$finish;
end
// Monitor $time
initial begin
$monitor("Time: %0t", $time);
end
endmodule
68 changes: 68 additions & 0 deletions Vcs
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#!/bin/bash

# Check if exactly one argument is provided
if [ "$#" -ne 1 ]; then
echo "Usage: $0 <module_name>"
exit 1
fi

module_name="$1"

dir_exists=0
tb_exists=0

# Check if directory does not exist
if [ ! -d "$module_name" ]; then
# Create directory with the name provided
mkdir "$module_name"
echo "Directory '$module_name' created."
else
dir_exists=1
fi


sed -i 's/`timescale.*//g' ${module_name}.sv

sed -i '1i\`timescale 1ns/100ps' ${module_name}.sv
## Comment out following for disabling DDR
# sed -i -E 's/(always @\(posedge (.*)_clkp).*/\1 or posedge \2_clkn) begin/g' ${module_name}.sv
# sed -i -E 's/(always @\(posedge (.*)_clk_800).*/\1 or negedge \2_clk_800) begin/g' ${module_name}.sv
# Move module_name.sv into the newly created directory if it exists and if directory was just created or file does not exist in the directory
# module_name.sv will always be overridden if there exists a module_name.sv in base dir
if [ -f "${module_name}.sv" ]; then
cp "${module_name}.sv" "$module_name/"
cp "${module_name}.anno.json" "$module_name/"
cp "${module_name}.fir" "$module_name/"
echo "Moved ${module_name} files into ${module_name}/"
fi


# Check if tb_module_name.sv does not exist before creating it
if [ ! -f "${module_name}/tb_${module_name}.sv" ]; then
cd ${module_name}/
perl ../generate_tb.pl "${module_name}.sv"
echo "Testbench for ${module_name} generated. Please complete tb_${module_name}.sv before running VCS."

else
tb_exists=1
fi



# Execute command if directory and tb file exist or after creating them
if [ $dir_exists -eq 1 ] && [ $tb_exists -eq 1 ]; then
echo "Executing VCS. on ${module_name}"
cd ${module_name}/
pwd
# Additional .sv files
resource_dir="../src/main/resources/vsrc/"
src_dir="./"

vcs -full64 -sverilog +incdir+$(dirname) +v2k -debug_all $(find $src_dir $resource_dir -name "*.sv") -o simv
./simv
else
echo "Setup completed. Complete tb_${module_name}.sv, then call this again to run VCS."
fi

#vcs -sverilog +incdir+$(dirname) tb_AsyncFifoStefan.sv AsyncFifoStefan.sv -o simv
#./simv
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