shakedown: wave 7: roadmap completion (non-accel / memory / GPU phases, 14/16 thermal, M1-M4 + Intel calibrations)#4
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…floor, 14/16 thermal classes Phase 4b reuses cpu-variance.sh with WORKLOAD=blake2b (opt-in --noaccel). Phase 12 memory-bandwidth.sh (multi-threaded ctypes.memmove, info). Phase 13 gpu-variance.sh (opt-in --gpu, compiles Metal via swiftc at runtime, skips gracefully). SSD warn-only floor (<500 MB/s, cache dropped). active-cooled-pro split into -14/-16 with the bare class kept as a 16-equivalent alias. Orchestrator wires all three new phases (always-emitted keys, opt-in as skipped stubs); CI REQUIRED_PHASES updated.
Schema bumped to 1.2 with phase detail sections for 12/4b/13 and a version-history entry. README phase table + rewritten roadmap. Pass-Fail Criteria gains -14/-16 threshold tables and a calibration-benchmarks section. SECURITY.md discloses the opt-in --gpu compile. New Verification/per-core-pinning.md documents the macOS no-affinity findings. CHANGELOG wave-7 entry with comparability notes.
Added examples/{m1-2020,m2-2022,m3-2023,m4-2024,intel-2016}/ calibration folders (overview, per-issue notes, sources) in the m5-2026 format, from researched and source-verified defect data. Representative presets: macbook-air-m1, macbook-air-m2, mbp-14-m3-pro, mac-mini-m4; mbp-16-intel-2019 repointed at examples/intel-2016; mbp-14/16 m5 presets set the new -14/-16 chassis classes.
The wave-5 cleanup killed em dashes in the docs but missed the scripts, the CI workflow, the run shim, and the issue template (about 100 left). Replace them per the voice rules: file-header and label lines get a colon, asides and clause joins get a comma or parens. En-dash ranges, the multiplication sign, ellipses, and arrows are left as-is. Pure punctuation: 101 lines changed, no logic touched, scripts still shellcheck-clean and the Python heredocs still parse.
…4 TB5 label) Adversarial review of the calibration prose against the verified research data surfaced two minor accuracy fixes: drop an unsourced 'hairline crack' origin detail from the M1 Air display-lines symptom (the lines themselves are sourced, the crack origin was not on the cited page), and relabel the M4 Thunderbolt 5 item from single-source to community-sourced/multiple-report (its verified confidence is multi-report, just not press/Apple-confirmed). m2 and m3 reviewed clean; the intel-2016 Flexgate wording was already correct.
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Wave 7 finishes off the v0.1 roadmap: three new phases, two methodology additions, M1-M4 + Intel generation calibrations, and schema 1.2.
New phases
--noaccel). Reusescpu-variance.shwithWORKLOAD=blake2b. BLAKE2b has no CPU crypto instruction, so it runs on the integer pipelines and catches batch defects SHA-NI / the Apple crypto engine hide. Same variance verdict logic, real pass/warn/fail when run.memory-bandwidth.sh). Multi-threadedctypes.memmoveover cache-busting buffers, one worker per P-core. Reports copy and touched (read+write) bandwidth plus run-to-run spread. Pure Python stdlib,infoverdict, RAM-guarded. A single thread can't saturate Apple Silicon's multi-channel controllers, so it's threaded the way STREAM uses OpenMP.--gpu). Compiles a small Metal kernel withswiftcat runtime (no binary shipped) and runs sustained FMA work. The one phase that isn't pure bash + Python stdlib; the Metal source is inline in the script, read it before running. Skips cleanly when swiftc or a Metal device is unavailable. Default./runstays pure-script; SECURITY.md discloses the opt-in compile.Methodology
active-cooled-pro-14(looser, throttles by design) andactive-cooled-pro-16(the prior strict thresholds). The bareactive-cooled-prostays valid as a 16-equivalent alias, so existing presets and submissions stay comparable. Auto-detect can't read screen size on Apple Silicon, so the precise class comes from--target.Verification/per-core-pinning.md): macOS has no public per-core affinity API (THREAD_AFFINITY_POLICYis ignored on Apple Silicon, QoS only steers between the P and E clusters);worker_imbalance_pct_per_iteris the partial mitigation.Generation calibrations
examples/{m1-2020,m2-2022,m3-2023,m4-2024,intel-2016}/, each a sourced defect landscape in the m5-2026 format (37 issues total, researched and source-verified, with confirmed vs anecdotal vs design-behavior clearly separated). Representative presets added (macbook-air-m1,macbook-air-m2,mbp-14-m3-pro,mac-mini-m4);mbp-16-intel-2019repointed at the Intel/T2 calibration.Schema and CI
Schema bumped to 1.2 (additive). The opt-in phases are always emitted as
skippedplaceholders by default, so default-run submissions still pass the audit. CIREQUIRED_PHASESgains the three new keys.Verification
Ran
./runend-to-end on an Intel MacBook Pro 16 (2019, macOS 14.4.1) in both the default and--noaccel --gpupaths. Memory bandwidth and the BLAKE2b pass produced real numbers; the GPU phase compiled and then skipped cleanly (no Metal device in a headless context, the exact path it must handle). All CI gates pass locally: shellcheck, heredocast.parse, JSON validation, markdown link resolution. No em dashes in any added line.Note
The pre-existing scripts, CI workflow, and issue template still carry em dashes from before the wave-5 docs cleanup (run-shakedown 26, thermal-load 25, cpu-variance 16, and a few more). This wave added none and reduced cpu-variance's count, but a dedicated sweep across the scripts would finish the job. Easy follow-up if you want it.