MIPS_32bit_SCDP_Verilog

An implementation of 32-bits MIPS Single Cycle Datapath in Verilog HDL.

MIPS Verilog

Name		Name	Last commit message	Last commit date
Latest commit History 8 Commits
ALU.v		ALU.v
ALU_Control.v		ALU_Control.v
ControlUnit.v		ControlUnit.v
DataMemory.v		DataMemory.v
README.md		README.md
RegisterFile.v		RegisterFile.v
SignExtension.v		SignExtension.v
adder.v		adder.v
adder_4.v		adder_4.v
ag.v		ag.v
datamemory.txt		datamemory.txt
instMemory.v		instMemory.v
jump_targer_add.v		jump_targer_add.v
main_MIPS_32b.v		main_MIPS_32b.v
main_testbench.v		main_testbench.v
mux_2x1_32bit.v		mux_2x1_32bit.v
mux_2x_1.v		mux_2x_1.v
runningInstruction.txt		runningInstruction.txt
shift_left_by2.v		shift_left_by2.v
shift_left_by2_26b.v		shift_left_by2_26b.v
unnamed.gif		unnamed.gif

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