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vakeesank99/README.md

MasterHead

Hi 👋, I'm Vakeesan

Final year student of Electronic & Telecommunication Engineering at University of Moratuwa

Interested in FPGA, ASIC SoC designing and Machine learning

Electronic

vakeesank99

Connect with me:

vakeesan karunanithy vakeesan karunanithy @vakeesank99 learn99

Languages and Tools:

arduino c cplusplus git illustrator matlab opencv photoshop python tensorflow

vakeesank99

Pinned Loading

  1. flower102classifier flower102classifier Public

    Jupyter Notebook

  2. Image_processing_on_ZYNQ Image_processing_on_ZYNQ Public

    convolution based image processing tasks can be applicable

    Verilog

  3. Matrix_multiplication_ip Matrix_multiplication_ip Public

    This is matrix multiplication ip for vivado 2018.3 design flow using zybo board. you can find both verilog and SDK files here

    SystemVerilog

  4. MIPS_simple_implementation MIPS_simple_implementation Public

    Whole design was inspired from the book 'Digital design and computer architecture.'

    Verilog 1