Refactor sync functions

src/sys/ata.rs

@@ -100,7 +100,7 @@ impl Bus {
     }
 
     fn wait(&mut self, ns: u64) {
-        sys::clk::nanowait(ns);
+        sys::clk::wait(ns);
     }
 
     fn clear_interrupt(&mut self) -> u8 {
@@ -164,7 +164,7 @@ impl Bus {
             // Bit 7 => 1
             self.drive_register.write(0xA0 | (drive << 4))
         }
-        sys::clk::nanowait(400); // Wait at least 400 ns
+        sys::clk::wait(400); // Wait at least 400 ns
         self.poll(Status::BSY, false)?;
         self.poll(Status::DRQ, false)?;
         Ok(())

src/sys/clk/mod.rs

@@ -2,13 +2,13 @@ mod cmos;
 mod boot;
 mod epoch;
 mod rtc;
-mod sleep;
+mod sync;
 mod timer;
 
 pub use boot::{boot_time, BootTime};
 pub use epoch::{epoch_time, EpochTime};
 pub use rtc::RTC;
-pub use sleep::{sleep, nanowait, halt};
+pub use sync::{halt, sleep, wait};
 pub use timer::{ticks, pit_frequency, set_pit_frequency};
 
 use crate::api;

src/sys/clk/sleep.rs → src/sys/clk/sync.rs

@@ -3,6 +3,9 @@ use super::timer;
 
 use x86_64::instructions::interrupts;
 
+/// Halts the CPU until the next interrupt.
+///
+/// This function preserves interrupt state.
 pub fn halt() {
     let disabled = !interrupts::are_enabled();
     interrupts::enable_and_hlt();
@@ -11,17 +14,24 @@ pub fn halt() {
     }
 }
 
+/// Sleeps for the specified number of seconds.
+///
+/// This function works by repeatedly halting the CPU until the time is
+/// elapsed.
 pub fn sleep(seconds: f64) {
     let start = boot::boot_time();
     while boot::boot_time() - start < seconds {
         halt();
     }
 }
 
-pub fn nanowait(nanoseconds: u64) {
+/// Waits for the specified number of nanoseconds.
+///
+/// This function use a busy-wait loop with the `RDTSC` and `PAUSE`
+/// instructions.
+pub fn wait(nanoseconds: u64) {
+    let delta = nanoseconds * timer::tsc_frequency();
     let start = timer::tsc();
-    let freq = timer::tsc_frequency();
-    let delta = nanoseconds * freq;
     while timer::tsc() - start < delta {
         core::hint::spin_loop();
     }

src/sys/clk/timer.rs

@@ -1,4 +1,4 @@
-use super::sleep;
+use super::sync;
 use super::cmos::CMOS;
 
 use crate::sys;
@@ -86,7 +86,7 @@ pub fn init() {
     // TSC timmer
     let calibration_time = 250_000; // 0.25 seconds
     let a = tsc();
-    sleep::sleep(calibration_time as f64 / 1e6);
+    sync::sleep(calibration_time as f64 / 1e6);
     let b = tsc();
     TSC_FREQUENCY.store((b - a) / calibration_time, Ordering::Relaxed);
 }

src/sys/net/nic/e1000.rs

@@ -168,7 +168,7 @@ impl Device {
         // Reset device
         let ctrl = self.read(REG_CTRL);
         self.write(REG_CTRL, ctrl | CTRL_RST); // Reset
-        sys::clk::nanowait(500); // TODO: How long should we wait?
+        sys::clk::wait(500); // TODO: How long should we wait?
 
         // Disable interrupts again
         self.write(REG_IMC, 0xFFFF);