[Hardware][Intel] fp8 kv cache support for CPU #5492

jikunshang · 2024-06-13T07:52:25Z

FILL IN THE PR DESCRIPTION HERE

Add FP8 kv cache for Intel CPU.

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mgoin · 2024-06-13T16:43:57Z

cmake/cpu_extension.cmake

@@ -43,7 +43,7 @@ if (AVX512_FOUND)
        "-mavx512dq")

    find_isa(${CPUINFO} "avx512_bf16" AVX512BF16_FOUND)
-    if (AVX512BF16_FOUND OR ENABLE_AVX512BF16)
+    if (AVX512BF16_FOUND AND ENABLE_AVX512BF16)


I think we want to compile for AVX512BF16 if we simply find it, not if we find it and force it

mgoin · 2024-06-13T16:48:02Z

csrc/cpu/attention.cpp


  constexpr static int TOKEN_PER_GROUP = k_load_vec_type::get_elem_num() / x;
  constexpr static int MAX_GROUP_NUM = 16 / TOKEN_PER_GROUP;
  constexpr static int UNROLL_GROUP_NUM = MAX_GROUP_NUM / 4;

-  static_assert(MAX_GROUP_NUM == 8 || MAX_GROUP_NUM == 4);


Why aren't these asserts valid anymore?

mgoin · 2024-06-13T16:52:21Z

csrc/cpu/attention.cpp

@@ -22,6 +22,16 @@ struct KernelVecType<float> {
  using v_load_vec_type = vec_op::FP32Vec16;
 };

+template <>
+struct KernelVecType<float, cpu_fp8> {


It isn't immediately clear that cpu_fp8 is treated as a type since the PyTorch types use PascalCase - maybe at least adding a _t such as cpu_fp8_t or CpuFP8 or FP8Cpu?

mgoin · 2024-06-13T16:55:28Z

csrc/cpu/attention.cpp

+        });
+  } else if (kv_cache_dtype == "fp8") {
+    if (query.dtype() == at::ScalarType::Float) {
+      CALL_V1_KERNEL_LAUNCHER_BLOCK_SIZE(float, cpu_fp8, true);


Why do you need this IS_FP8_KV_CACHE boolean in paged_attention_v1 but not in paged_attention_v2? It seems like it could be deduced by checking the cache_t within the kernel and this would bode better for future cache types being used.

mgoin · 2024-06-13T16:57:18Z

csrc/cpu/cpu_types.hpp

@@ -5,6 +5,10 @@
 #include <immintrin.h>
 #include <torch/all.h>

+#include "fp8_utils.h"
+
+typedef uint8_t cpu_fp8;


Calling out again that I think the name of this type doesn't seem like a type.

mgoin · 2024-06-13T17:00:55Z

csrc/cpu/fp8_utils.h

+  return _mm512_slli_epi16(_mm512_cvtepi8_epi16(a), 8);
+}
+
+static inline __m256i _mm256_cvte5m2_fp16(__m128i a) {


For all these function signatures that have just e5m2 to signify fp8e5m2, I think it would be more clear to include the fp8

mgoin · 2024-06-13T17:01:36Z

csrc/cpu/fp8_utils.h

+  const __m512i a_ = _mm512_inserti64x4(
+      _mm512_inserti64x4(_mm512_setzero_si512(), b, 0), a, 1);
+  const __mmask32 maska1_ = _mm512_cmp_epi16_mask(_mm512_and_si512(a_, vnaninf),
+                                                  vnaninf, _MM_CMPINT_NE);
+  const __mmask32 maska2_ = _mm512_cmp_epi16_mask(
+      _mm512_and_si512(a_, vfixupmask), vfixupmask, _MM_CMPINT_EQ);
+  const __mmask32 maska3_ =
+      _mm512_cmp_epi16_mask(_mm512_and_si512(a_, _mm512_set1_epi16(0x7FFF)),
+                            vsatuval, _MM_CMPINT_NLE);
+  __m512i vExp_ = _mm512_sub_epi16(
+      _mm512_srli_epi16(_mm512_and_si512(a_, vnaninf), 10), vExp_fp16);
+  vExp_ = _mm512_slli_epi16(_mm512_add_epi16(vExp_, vExp_e5m2), 10);
+  __m512i a_rne_ = _mm512_or_si512(vExp_, _mm512_and_si512(a_, vsMant));
+  a_rne_ = _mm512_mask_add_epi16(
+      a_rne_, maska1_, a_rne_,
+      _mm512_mask_add_epi16(vrneadd, maska2_, vrneadd, vfixup));
+  a_rne_ = _mm512_mask_mov_epi16(
+      a_rne_, maska3_,
+      _mm512_or_si512(_mm512_and_si512(a_rne_, vinfval), vsatuval));
+  a_rne_ = _mm512_mask_mov_epi16(a_rne_, ~maska1_, vinfval);
+  return _mm512_cvtepi16_epi8(_mm512_srli_epi16(a_rne_, 8));


Any additional function header or inline comments would be appreciated!

mgoin · 2024-06-13T17:06:00Z

csrc/cpu/fp8_utils.h

+  return _mm512_mask_mov_epi16(a_, mask1_, vinfval);
+}
+
+static inline void cvt_fp16_e5m2_noINF_rne_intrinsic(


What is the difference between noinf and noINF?

mgoin · 2024-06-13T17:11:19Z

csrc/cpu/fp8_utils.h

+static inline void cast_fp16xn_to_fp8xn(const short* __restrict__ in,
+                                        unsigned char* out, int n) {
+  cvt_fp16_e5m2_noINF_rne_intrinsic(in, out, n);
+}
+
+static inline void cast_fp32xn_to_fp8xn(const float* __restrict__ in,
+                                        float* out, int n) {
+  cvt_fp32_e5m2_noinf_rne_intrinsic(in, out, n, 0);
+}


It seems you aren't getting any reuse out of these functions, why not inline the body?

mgoin · 2024-06-13T17:14:36Z

vllm/attention/backends/torch_sdpa.py

-        if kv_cache_dtype != "auto":
-            raise NotImplementedError(
-                "Torch SDPA backend does not support FP8 KV cache. "
-                "Please use xFormers backend instead.")


This is only implemented for CPU usage of the Torch SPDA backend, right? Would fp8 kv cache work if we used CUDA with the SPDA backend, for instance?

mgoin

Also cc @comaniac !

comaniac · 2024-06-13T18:36:33Z

csrc/cpu/attention.cpp

+          CALL_V1_KERNEL_LAUNCHER_BLOCK_SIZE(scalar_t, scalar_t, false);
+          CPU_KERNEL_GUARD_OUT(paged_attention_v1_impl)
+        });
+  } else if (kv_cache_dtype == "fp8") {


It'd be better to align with the general interface. We now support fp8, fp8_e4m3 and fp8_e5m2. Note that fp8 defaults to fp8_e4m3. Please cover all cases and throw an error for unsupported cases.

bigPYJ1151 mentioned this pull request Jun 13, 2024

[RFC] Initial Support for CPUs #3654

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4 tasks

WoosukKwon added the x86 CPU label Jun 13, 2024

mgoin reviewed Jun 13, 2024

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comaniac reviewed Jun 13, 2024

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jikunshang marked this pull request as draft June 17, 2024 02:55

jikunshang force-pushed the cpu_fp8_kv_cache branch from b8b94af to 174c369 Compare July 1, 2024 05:31

fp8 kv cache support

174c369

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[Hardware][Intel] fp8 kv cache support for CPU #5492

[Hardware][Intel] fp8 kv cache support for CPU #5492

jikunshang commented Jun 13, 2024

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comaniac Jun 13, 2024

[Hardware][Intel] fp8 kv cache support for CPU #5492

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[Hardware][Intel] fp8 kv cache support for CPU #5492

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jikunshang commented Jun 13, 2024

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