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Fix right shifts and sltu[i] instructions #8

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Fix right shifts and sltu[i] instructions #8

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16 changes: 8 additions & 8 deletions riscvmodel/insn.py
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Original file line number Diff line number Diff line change
Expand Up @@ -163,7 +163,7 @@ def execute(self, model: Model):
@isa("sltiu", RV32I, opcode=0b0010011, funct3=0b011)
class InstructionSLTIU(InstructionIType):
def execute(self, model: Model):
if model.state.intreg[self.rs1].unsigned() < int(self.imm):
if model.state.intreg[self.rs1].unsigned() < int(self.imm) & 0xFFFFFFFF:
model.state.intreg[self.rd] = 1
else:
model.state.intreg[self.rd] = 0
Expand Down Expand Up @@ -203,7 +203,7 @@ def execute(self, model: Model):
@isa("srai", RV32I, opcode=0b0010011, funct3=0b101, funct7=0b0100000)
class InstructionSRAI(InstructionISType):
def execute(self, model: Model):
model.state.intreg[self.rd] = model.state.intreg[self.rs1] >> self.shamt
model.state.intreg[self.rd] = (model.state.intreg[self.rs1] & 0xFFFFFFFF) >> self.shamt


@isa("add", RV32I, opcode=0b0110011, funct3=0b000, funct7=0b0000000)
Expand Down Expand Up @@ -236,12 +236,12 @@ def execute(self, model: Model):

@isa("sltu", RV32I, opcode=0b0110011, funct3=0b011, funct7=0b0000000)
class InstructionSLTU(InstructionRType):
def execute(self, state: State):
if state.intreg[self.rs1].unsigned() < state.intreg[
def execute(self, model: Model):
if model.state.intreg[self.rs1].unsigned() < model.state.intreg[
self.rs2].unsigned():
state.intreg[self.rd] = 1
model.state.intreg[self.rd] = 1
else:
state.intreg[self.rd] = 0
model.state.intreg[self.rd] = 0


@isa("xor", RV32I, opcode=0b0110011, funct3=0b100, funct7=0b0000000)
Expand All @@ -253,8 +253,8 @@ def execute(self, model: Model):
@isa("srl", RV32I, opcode=0b0110011, funct3=0b101, funct7=0b0000000)
class InstructionSRL(InstructionRType):
def execute(self, model: Model):
src = model.state.intreg[self.rs1]
shift = model.state.intreg[self.rs2] & 0x1f
src = model.state.intreg[self.rs1].unsigned()
shift = int(model.state.intreg[self.rs2] & 0x1f)
model.state.intreg[self.rd] = src >> shift


Expand Down
5 changes: 2 additions & 3 deletions riscvmodel/types.py
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Original file line number Diff line number Diff line change
Expand Up @@ -226,11 +226,10 @@ def __lshift__(self, other):

def __rshift__(self, other):
new = Register(self.bits)
value = (self.value + 2**self.bits) if self.value < 0 else self.value
if isinstance(other, int):
new.set(value >> other)
new.set(self.value >> other)
elif isinstance(other, (Register, Immediate)):
new.set(value >> other.value)
new.set(self.value >> other.value)
else:
raise TypeError("unsupported operand type for Register >>: {}".format(other.__class__))
return new
Expand Down