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feat(motor driver): integration changes to dts
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dts file changes to add peripheral support for motor driver

Signed-off-by: Srikar Chintapalli <[email protected]>
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@sri9311
sri9311 committed Jan 29, 2025
1 parent f01a485 commit 0310447
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Showing 4 changed files with 110 additions and 89 deletions.
20 changes: 19 additions & 1 deletion boards/tfh/diamond_main/diamond_main.dts
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Original file line number Diff line number Diff line change
Expand Up @@ -70,6 +70,8 @@
supply-vbat-sw-enable-gpios = <&gpio_exp_pwr_brd 12 GPIO_ACTIVE_HIGH>;
front-unit-pvcc-enabled-gpios = <&gpio_exp_front_unit 0 GPIO_ACTIVE_HIGH>;

polarizer-direction-gpios = <&gpio_exp1 1 GPIO_ACTIVE_HIGH>;

// The signals FUSE_RST and FUSE_ACTIVE are available only on Front Unit 6.0 (PoC1) and 6.1 (PoC2)
// On Front Unit 6.2 (B3) the signal EN_5V_SWITCHED is connected to the port expander pin P02 instead.
front-unit-fuse-reset-gpios = <&gpio_exp_front_unit 2 GPIO_ACTIVE_LOW>; // PoC1 & PoC2 only
Expand Down Expand Up @@ -797,6 +799,13 @@
pinctrl-names = "default";
channels = <3>;
};

polarizer_step: polarizer_step {
compatible = "worldcoin,stm32-pwm";
pinctrl-0 = <&tim2_ch2_pd4>;
pinctrl-names = "default";
channels = <2>;
};
};

&timers3 {
Expand Down Expand Up @@ -1041,7 +1050,8 @@
&spi1 {
pinctrl-0 = <&spi1_sck_pa5 &spi1_miso_pa6 &spi1_mosi_pa7>;
pinctrl-names = "default";
cs-gpios = <&gpioa 3 GPIO_ACTIVE_LOW>;
cs-gpios = <&gpioa 3 GPIO_ACTIVE_LOW>,
<&gpio_exp1 0 GPIO_ACTIVE_LOW>; /* CS on I/O expander */
status = "okay";

motion_controller: motion_controller@0 {
Expand All @@ -1050,6 +1060,14 @@
spi-max-frequency = <4000000>;
status = "okay";
};

polarizer_controller: polarizer_controller@1 {
compatible = "zephyr,spi-device";
reg = <1>; /* This will use the I/O expander CS */
spi-max-frequency = <4000000>;
spi-mode = <0>;
status = "okay";
};
};

&spi2 {
Expand Down
3 changes: 3 additions & 0 deletions main_board/CMakeLists.txt
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Original file line number Diff line number Diff line change
Expand Up @@ -88,6 +88,9 @@ list(APPEND SOURCES_FILES
src/optics/liquid_lens/liquid_lens.c
src/optics/mirror/mirror.c

src/optics/polarizer/drv8434/drv8434_private.c
src/optics/polarizer/drv8434/drv8434.c

src/power/boot/boot.c

src/runner/runner.c
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6 changes: 3 additions & 3 deletions main_board/src/optics/polarizer/drv8434/drv8434.c
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Original file line number Diff line number Diff line change
Expand Up @@ -91,19 +91,19 @@ drv8434_read_config(void)
return ret_val;
}

ret_val = ret_val =
ret_val =
drv8434_private_reg_read(DRV8434_REG_CTRL3_ADDR, &g_drv8434_instance);
if (ret_val) {
return ret_val;
}

ret_val = ret_val =
ret_val =
drv8434_private_reg_read(DRV8434_REG_CTRL4_ADDR, &g_drv8434_instance);
if (ret_val) {
return ret_val;
}

ret_val = ret_val =
ret_val =
drv8434_private_reg_read(DRV8434_REG_CTRL7_ADDR, &g_drv8434_instance);
if (ret_val) {
return ret_val;
Expand Down
170 changes: 85 additions & 85 deletions main_board/src/optics/polarizer/drv8434/drv8434_private.c
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Original file line number Diff line number Diff line change
Expand Up @@ -15,91 +15,6 @@

#include "drv8434_private.h"

ret_code_t
drv8434_private_reg_read(uint8_t address, DRV8434_Instance_t *instance)
{
if (instance == NULL) {
return RET_ERROR_INVALID_PARAM;
}

if (!validate_register_operation(address, false)) {
return RET_ERROR_INVALID_ADDR;
}

uint16_t tx_word = 0;

// Load register address into tx word
tx_word =
tx_word | ((uint16_t)(address) << DRV8434_SPI_TX_ADDRESS_START_POS);

// Load r/w bit into tx word
tx_word = tx_word | ((uint16_t)(DRV8434_SPI_TX_RW_BIT_READ)
<< DRV8434_SPI_TX_RW_START_POS);

// Wipe TX and RX buffers before each operation
memset(instance->spi.rx_buffer, 0, sizeof(instance->spi.rx_buffer));
memset(instance->spi.tx_buffer, 0, sizeof(instance->spi.tx_buffer));

instance->spi.tx_buffer[0u] = (tx_word >> 8) & DRV8434_SPI_TX_LSB_MASK;
instance->spi.tx_buffer[1u] = tx_word & DRV8434_SPI_TX_LSB_MASK;

int ret = spi_transceive(instance->driver_cfg.spi_bus_controller,
&instance->driver_cfg.spi_cfg,
&instance->spi.tx_bufs, &instance->spi.rx_bufs);

if (ret) {
return RET_ERROR_BUSY;
}

instance->registers.fault.raw = instance->spi.rx_buffer[0u];

populate_shadow_register(address, instance->spi.rx_buffer[1u], instance);

return RET_SUCCESS;
}

ret_code_t
drv8434_private_reg_write(uint8_t address, uint8_t data,
DRV8434_Instance_t *instance)
{
if (instance == NULL) {
return RET_ERROR_INVALID_PARAM;
}

if (!validate_register_operation(address, false)) {
return RET_ERROR_INVALID_ADDR;
}

uint16_t tx_word = 0;

// Load register address into tx word
tx_word =
tx_word | ((uint16_t)(address) << DRV8434_SPI_TX_ADDRESS_START_POS);

// Load data into tx word
tx_word = tx_word | (uint16_t)(data);

// Wipe TX and RX buffers before each operation
memset(instance->spi.rx_buffer, 0, sizeof(instance->spi.rx_buffer));
memset(instance->spi.tx_buffer, 0, sizeof(instance->spi.tx_buffer));

instance->spi.tx_buffer[0u] = (tx_word >> 8) & DRV8434_SPI_TX_LSB_MASK;
instance->spi.tx_buffer[1u] = tx_word & DRV8434_SPI_TX_LSB_MASK;

int ret = spi_transceive(instance->driver_cfg.spi_bus_controller,
&instance->driver_cfg.spi_cfg,
&instance->spi.tx_bufs, &instance->spi.rx_bufs);

if (ret) {
return RET_ERROR_BUSY;
}

// Only care about fault status bits reported back
instance->registers.fault.raw = instance->spi.rx_buffer[0u];

return RET_SUCCESS;
}

/**
* @brief DRV8434 Register Operation Validity Check
*
Expand Down Expand Up @@ -197,3 +112,88 @@ populate_shadow_register(uint8_t address, uint8_t data,
}
return;
}

ret_code_t
drv8434_private_reg_read(uint8_t address, DRV8434_Instance_t *instance)
{
if (instance == NULL) {
return RET_ERROR_INVALID_PARAM;
}

if (!validate_register_operation(address, false)) {
return RET_ERROR_INVALID_ADDR;
}

uint16_t tx_word = 0;

// Load register address into tx word
tx_word =
tx_word | ((uint16_t)(address) << DRV8434_SPI_TX_ADDRESS_START_POS);

// Load r/w bit into tx word
tx_word = tx_word | ((uint16_t)(DRV8434_SPI_TX_RW_BIT_READ)
<< DRV8434_SPI_TX_RW_START_POS);

// Wipe TX and RX buffers before each operation
memset(instance->spi.rx_buffer, 0, sizeof(instance->spi.rx_buffer));
memset(instance->spi.tx_buffer, 0, sizeof(instance->spi.tx_buffer));

instance->spi.tx_buffer[0u] = (tx_word >> 8) & DRV8434_SPI_TX_LSB_MASK;
instance->spi.tx_buffer[1u] = tx_word & DRV8434_SPI_TX_LSB_MASK;

int ret = spi_transceive(instance->driver_cfg.spi_bus_controller,
&instance->driver_cfg.spi_cfg,
&instance->spi.tx_bufs, &instance->spi.rx_bufs);

if (ret) {
return RET_ERROR_BUSY;
}

instance->registers.fault.raw = instance->spi.rx_buffer[0u];

populate_shadow_register(address, instance->spi.rx_buffer[1u], instance);

return RET_SUCCESS;
}

ret_code_t
drv8434_private_reg_write(uint8_t address, uint8_t data,
DRV8434_Instance_t *instance)
{
if (instance == NULL) {
return RET_ERROR_INVALID_PARAM;
}

if (!validate_register_operation(address, false)) {
return RET_ERROR_INVALID_ADDR;
}

uint16_t tx_word = 0;

// Load register address into tx word
tx_word =
tx_word | ((uint16_t)(address) << DRV8434_SPI_TX_ADDRESS_START_POS);

// Load data into tx word
tx_word = tx_word | (uint16_t)(data);

// Wipe TX and RX buffers before each operation
memset(instance->spi.rx_buffer, 0, sizeof(instance->spi.rx_buffer));
memset(instance->spi.tx_buffer, 0, sizeof(instance->spi.tx_buffer));

instance->spi.tx_buffer[0u] = (tx_word >> 8) & DRV8434_SPI_TX_LSB_MASK;
instance->spi.tx_buffer[1u] = tx_word & DRV8434_SPI_TX_LSB_MASK;

int ret = spi_transceive(instance->driver_cfg.spi_bus_controller,
&instance->driver_cfg.spi_cfg,
&instance->spi.tx_bufs, &instance->spi.rx_bufs);

if (ret) {
return RET_ERROR_BUSY;
}

// Only care about fault status bits reported back
instance->registers.fault.raw = instance->spi.rx_buffer[0u];

return RET_SUCCESS;
}

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