aarch64: access stack in pairs of registers#6
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yugr merged 2 commits intoyugr:masterfrom Sep 26, 2019
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On aarch64 CPUs load and store addresses have to be aligned to multiples of 16. Otherwise an exception is thrown and the application receives a SIGBUS. Unlike actual CPUs, QEMU does not care about alignment here. Use stp and ldp instructions for manipulating the stack in register pairs which automaticlly leads to appropriately aligned addresses. Signed-off-by: Josua Mayer <josua@solid-run.com>
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Thanks, merged. |
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On aarch64 CPUs load and store addresses have to be aligned to multiples
of 16. Otherwise an exception is thrown and the application receives a
SIGBUS. Unlike native CPUs, QEMU does not care about alignment here.
Use stp and ldp instructions for manipulating the stack in register
pairs which automaticlly leads to appropriately aligned addresses.
Signed-off-by: Josua Mayer josua@solid-run.com