Use relative path for BD references

[zaporozhets]

I noticed that write_project_tcl_git adds BD's Verilog references with full path. For example:

# Adding sources referenced in BDs, if not already added
if { [get_files dbg_bridge.v] == "" } {
  import_files -quiet -fileset sources_1 /home/taras/dev/yo/external/core_dbg_bridge/src_v/dbg_bridge.v
}
if { [get_files dbg_bridge_fifo.v] == "" } {
  import_files -quiet -fileset sources_1 /home/taras/dev/yo/external/core_dbg_bridge/src_v/dbg_bridge_fifo.v
}
if { [get_files dbg_bridge_uart.v] == "" } {
  import_files -quiet -fileset sources_1 /home/taras/dev/yo/external/core_dbg_bridge/src_v/dbg_bridge_uart.v
}
if { [get_files dbg_bridge_wrapper.v] == "" } {
  import_files -quiet -fileset sources_1 /home/taras/dev/yo/fpga/common/rtl/dbg_bridge_wrapper.v
}

So I made a tiny to add_references in write_project_tcl_git.tcl and it does the following:

# Adding sources referenced in BDs, if not already added
if { [get_files dbg_bridge.v] == "" } {
  import_files -quiet -fileset sources_1 ../../../external/core_dbg_bridge/src_v/dbg_bridge.v
}
if { [get_files dbg_bridge_fifo.v] == "" } {
  import_files -quiet -fileset sources_1 ../../../external/core_dbg_bridge/src_v/dbg_bridge_fifo.v
}
if { [get_files dbg_bridge_uart.v] == "" } {
  import_files -quiet -fileset sources_1 ../../../external/core_dbg_bridge/src_v/dbg_bridge_uart.v
}
if { [get_files dbg_bridge_wrapper.v] == "" } {
  import_files -quiet -fileset sources_1 ../../common/rtl/dbg_bridge_wrapper.v
}

Original post: barbedo#9 (comment)