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dts: arm: st: remove U suffix from "resets" arg in SoC DTSI files #97355

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Merged
merged 21 commits into from
Oct 14, 2025
Merged

dts: arm: st: remove U suffix from "resets" arg in SoC DTSI files #97355

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7468451
dts: bindings: reset: stm32: remove useless U suffix on bit position
etienne-lms Oct 10, 2025
b6e8bab
dts: arm: st: stm32c0: remove U suffix from "resets" in DTSI
etienne-lms Oct 10, 2025
9bfd3f9
dts: arm: st: stm32f0: remove U suffix from "resets" in DTSI
etienne-lms Oct 10, 2025
fa5817b
dts: arm: st: stm32f1: remove U suffix from "resets" in DTSI
etienne-lms Oct 10, 2025
dd0ae96
dts: arm: st: stm32f2: remove U suffix from "resets" in DTSI
etienne-lms Oct 10, 2025
2817f29
dts: arm: st: stm32f3: remove U suffix from "resets" in DTSI
etienne-lms Oct 10, 2025
f9b8041
dts: arm: st: stm32f4: remove U suffix from "resets" in DTSI
etienne-lms Oct 10, 2025
f116662
dts: arm: st: stm32f7: remove U suffix from "resets" in DTSI
etienne-lms Oct 10, 2025
49458e7
dts: arm: st: stm32g0: remove U suffix from "resets" in DTSI
etienne-lms Oct 10, 2025
1572df4
dts: arm: st: stm32g4: remove U suffix from "resets" in DTSI
etienne-lms Oct 10, 2025
b2dcba5
dts: arm: st: stm32h5: remove U suffix from "resets" in DTSI
etienne-lms Oct 10, 2025
a02949c
dts: arm: st: stm32h7: remove U suffix from "resets" in DTSI
etienne-lms Oct 10, 2025
330601b
dts: arm: st: stm32l0: remove U suffix from "resets" in DTSI
etienne-lms Oct 10, 2025
51a5c83
dts: arm: st: stm32l1: remove U suffix from "resets" in DTSI
etienne-lms Oct 10, 2025
2cd6d6c
dts: arm: st: stm32l4: remove U suffix from "resets" in DTSI
etienne-lms Oct 10, 2025
b64b603
dts: arm: st: stm32l5: remove U suffix from "resets" in DTSI
etienne-lms Oct 10, 2025
9bddce3
dts: arm: st: stm32mp1: remove U suffix from "resets" in DTSI
etienne-lms Oct 10, 2025
8af2fbb
dts: arm: st: stm32u0: remove U suffix from "resets" in DTSI
etienne-lms Oct 10, 2025
9968895
dts: arm: st: stm32wb: remove U suffix from "resets" in DTSI
etienne-lms Oct 10, 2025
27701a3
dts: arm: st: stm32wba: remove U suffix from "resets" in DTSI
etienne-lms Oct 10, 2025
73ab840
dts: arm: st: stm32wl: remove U suffix from "resets" in DTSI
etienne-lms Oct 10, 2025
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14 changes: 7 additions & 7 deletions dts/arm/st/c0/stm32c0.dtsi
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Original file line number Diff line number Diff line change
Expand Up @@ -303,7 +303,7 @@
compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40013800 0x400>;
clocks = <&rcc STM32_CLOCK(APB1_2, 14)>;
resets = <&rctl STM32_RESET(APB1H, 14U)>;
resets = <&rctl STM32_RESET(APB1H, 14)>;
interrupts = <27 0>;
status = "disabled";
};
Expand All @@ -312,7 +312,7 @@
compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40004400 0x400>;
clocks = <&rcc STM32_CLOCK(APB1, 17)>;
resets = <&rctl STM32_RESET(APB1L, 17U)>;
resets = <&rctl STM32_RESET(APB1L, 17)>;
interrupts = <28 0>;
status = "disabled";
};
Expand All @@ -322,7 +322,7 @@
reg = <0x40012C00 0x400>;
clocks = <&rcc STM32_CLOCK(APB1_2, 11)>,
<&rcc STM32_SRC_TIMPCLK1 NO_SEL>;
resets = <&rctl STM32_RESET(APB1H, 11U)>;
resets = <&rctl STM32_RESET(APB1H, 11)>;
interrupts = <13 0>, <14 0>;
interrupt-names = "brk_up_trg_com", "cc";
st,prescaler = <0>;
Expand All @@ -345,7 +345,7 @@
reg = <0x40000400 0x400>;
clocks = <&rcc STM32_CLOCK(APB1, 1)>,
<&rcc STM32_SRC_TIMPCLK1 NO_SEL>;
resets = <&rctl STM32_RESET(APB1L, 1U)>;
resets = <&rctl STM32_RESET(APB1L, 1)>;
interrupts = <16 0>;
interrupt-names = "global";
st,prescaler = <0>;
Expand All @@ -368,7 +368,7 @@
reg = <0x40002000 0x400>;
clocks = <&rcc STM32_CLOCK(APB1_2, 15)>,
<&rcc STM32_SRC_TIMPCLK1 NO_SEL>;
resets = <&rctl STM32_RESET(APB1H, 15U)>;
resets = <&rctl STM32_RESET(APB1H, 15)>;
interrupts = <19 0>;
interrupt-names = "global";
st,prescaler = <0>;
Expand All @@ -391,7 +391,7 @@
reg = <0x40014400 0x400>;
clocks = <&rcc STM32_CLOCK(APB1_2, 17)>,
<&rcc STM32_SRC_TIMPCLK1 NO_SEL>;
resets = <&rctl STM32_RESET(APB1H, 17U)>;
resets = <&rctl STM32_RESET(APB1H, 17)>;
interrupts = <21 0>;
interrupt-names = "global";
st,prescaler = <0>;
Expand All @@ -414,7 +414,7 @@
reg = <0x40014800 0x400>;
clocks = <&rcc STM32_CLOCK(APB1_2, 18)>,
<&rcc STM32_SRC_TIMPCLK1 NO_SEL>;
resets = <&rctl STM32_RESET(APB1H, 18U)>;
resets = <&rctl STM32_RESET(APB1H, 18)>;
interrupts = <22 0>;
interrupt-names = "global";
st,prescaler = <0>;
Expand Down
12 changes: 6 additions & 6 deletions dts/arm/st/f0/stm32f0.dtsi
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Original file line number Diff line number Diff line change
Expand Up @@ -176,7 +176,7 @@
compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40013800 0x400>;
clocks = <&rcc STM32_CLOCK(APB2, 14)>;
resets = <&rctl STM32_RESET(APB2, 14U)>;
resets = <&rctl STM32_RESET(APB2, 14)>;
interrupts = <27 0>;
status = "disabled";
};
Expand Down Expand Up @@ -237,7 +237,7 @@
reg = <0x40012c00 0x400>;
clocks = <&rcc STM32_CLOCK(APB2, 11)>,
<&rcc STM32_SRC_TIMPCLK1 NO_SEL>;
resets = <&rctl STM32_RESET(APB2, 11U)>;
resets = <&rctl STM32_RESET(APB2, 11)>;
interrupts = <13 0>, <14 0>;
interrupt-names = "brk_up_trg_com", "cc";
st,prescaler = <0>;
Expand All @@ -255,7 +255,7 @@
reg = <0x40000400 0x400>;
clocks = <&rcc STM32_CLOCK(APB1, 1)>,
<&rcc STM32_SRC_TIMPCLK1 NO_SEL>;
resets = <&rctl STM32_RESET(APB1, 1U)>;
resets = <&rctl STM32_RESET(APB1, 1)>;
interrupts = <16 0>;
interrupt-names = "global";
st,prescaler = <0>;
Expand All @@ -278,7 +278,7 @@
reg = <0x40002000 0x400>;
clocks = <&rcc STM32_CLOCK(APB1, 8)>,
<&rcc STM32_SRC_TIMPCLK1 NO_SEL>;
resets = <&rctl STM32_RESET(APB1, 8U)>;
resets = <&rctl STM32_RESET(APB1, 8)>;
interrupts = <19 0>;
interrupt-names = "global";
st,prescaler = <0>;
Expand All @@ -301,7 +301,7 @@
reg = <0x40014400 0x400>;
clocks = <&rcc STM32_CLOCK(APB2, 17)>,
<&rcc STM32_SRC_TIMPCLK1 NO_SEL>;
resets = <&rctl STM32_RESET(APB2, 17U)>;
resets = <&rctl STM32_RESET(APB2, 17)>;
interrupts = <21 0>;
interrupt-names = "global";
st,prescaler = <0>;
Expand All @@ -324,7 +324,7 @@
reg = <0x40014800 0x400>;
clocks = <&rcc STM32_CLOCK(APB2, 18)>,
<&rcc STM32_SRC_TIMPCLK1 NO_SEL>;
resets = <&rctl STM32_RESET(APB2, 18U)>;
resets = <&rctl STM32_RESET(APB2, 18)>;
interrupts = <22 0>;
interrupt-names = "global";
st,prescaler = <0>;
Expand Down
6 changes: 3 additions & 3 deletions dts/arm/st/f0/stm32f030X8.dtsi
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Original file line number Diff line number Diff line change
Expand Up @@ -22,7 +22,7 @@
compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40004400 0x400>;
clocks = <&rcc STM32_CLOCK(APB1, 17)>;
resets = <&rctl STM32_RESET(APB1, 17U)>;
resets = <&rctl STM32_RESET(APB1, 17)>;
interrupts = <28 0>;
status = "disabled";
};
Expand Down Expand Up @@ -54,7 +54,7 @@
reg = <0x40001000 0x400>;
clocks = <&rcc STM32_CLOCK(APB1, 4)>,
<&rcc STM32_SRC_TIMPCLK1 NO_SEL>;
resets = <&rctl STM32_RESET(APB1, 4U)>;
resets = <&rctl STM32_RESET(APB1, 4)>;
interrupts = <17 0>;
interrupt-names = "global";
st,prescaler = <0>;
Expand All @@ -66,7 +66,7 @@
reg = <0x40014000 0x400>;
clocks = <&rcc STM32_CLOCK(APB2, 16)>,
<&rcc STM32_SRC_TIMPCLK1 NO_SEL>;
resets = <&rctl STM32_RESET(APB2, 16U)>;
resets = <&rctl STM32_RESET(APB2, 16)>;
interrupts = <20 0>;
interrupt-names = "global";
st,prescaler = <0>;
Expand Down
10 changes: 5 additions & 5 deletions dts/arm/st/f0/stm32f030Xc.dtsi
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Original file line number Diff line number Diff line change
Expand Up @@ -30,7 +30,7 @@
compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40004800 0x400>;
clocks = <&rcc STM32_CLOCK(APB1, 18)>;
resets = <&rctl STM32_RESET(APB1, 18U)>;
resets = <&rctl STM32_RESET(APB1, 18)>;
interrupts = <29 0>;
status = "disabled";
};
Expand All @@ -39,7 +39,7 @@
compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40004c00 0x400>;
clocks = <&rcc STM32_CLOCK(APB1, 19)>;
resets = <&rctl STM32_RESET(APB1, 19U)>;
resets = <&rctl STM32_RESET(APB1, 19)>;
interrupts = <29 0>;
status = "disabled";
};
Expand All @@ -48,7 +48,7 @@
compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40005000 0x400>;
clocks = <&rcc STM32_CLOCK(APB1, 20)>;
resets = <&rctl STM32_RESET(APB1, 20U)>;
resets = <&rctl STM32_RESET(APB1, 20)>;
interrupts = <29 0>;
status = "disabled";
};
Expand All @@ -57,7 +57,7 @@
compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40011400 0x400>;
clocks = <&rcc STM32_CLOCK(APB2, 5)>;
resets = <&rctl STM32_RESET(APB2, 5U)>;
resets = <&rctl STM32_RESET(APB2, 5)>;
interrupts = <29 0>;
status = "disabled";
};
Expand All @@ -67,7 +67,7 @@
reg = <0x40001400 0x400>;
clocks = <&rcc STM32_CLOCK(APB1, 5)>,
<&rcc STM32_SRC_TIMPCLK1 NO_SEL>;
resets = <&rctl STM32_RESET(APB1, 5U)>;
resets = <&rctl STM32_RESET(APB1, 5)>;
interrupts = <18 0>;
interrupt-names = "global";
st,prescaler = <0>;
Expand Down
2 changes: 1 addition & 1 deletion dts/arm/st/f0/stm32f031.dtsi
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Original file line number Diff line number Diff line change
Expand Up @@ -15,7 +15,7 @@
reg = <0x40000000 0x400>;
clocks = <&rcc STM32_CLOCK(APB1, 0)>,
<&rcc STM32_SRC_TIMPCLK1 NO_SEL>;
resets = <&rctl STM32_RESET(APB1, 0U)>;
resets = <&rctl STM32_RESET(APB1, 0)>;
interrupts = <15 0>;
interrupt-names = "global";
st,prescaler = <0>;
Expand Down
4 changes: 2 additions & 2 deletions dts/arm/st/f0/stm32f042.dtsi
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Original file line number Diff line number Diff line change
Expand Up @@ -23,7 +23,7 @@
compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40004400 0x400>;
clocks = <&rcc STM32_CLOCK(APB1, 17)>;
resets = <&rctl STM32_RESET(APB1, 17U)>;
resets = <&rctl STM32_RESET(APB1, 17)>;
interrupts = <28 0>;
status = "disabled";
};
Expand Down Expand Up @@ -51,7 +51,7 @@
reg = <0x40014000 0x400>;
clocks = <&rcc STM32_CLOCK(APB2, 16)>,
<&rcc STM32_SRC_TIMPCLK1 NO_SEL>;
resets = <&rctl STM32_RESET(APB2, 16U)>;
resets = <&rctl STM32_RESET(APB2, 16)>;
interrupts = <20 0>;
interrupt-names = "global";
st,prescaler = <0>;
Expand Down
6 changes: 3 additions & 3 deletions dts/arm/st/f0/stm32f051.dtsi
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Original file line number Diff line number Diff line change
Expand Up @@ -14,7 +14,7 @@
compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40004400 0x400>;
clocks = <&rcc STM32_CLOCK(APB1, 17)>;
resets = <&rctl STM32_RESET(APB1, 17U)>;
resets = <&rctl STM32_RESET(APB1, 17)>;
interrupts = <28 0>;
status = "disabled";
};
Expand Down Expand Up @@ -46,7 +46,7 @@
reg = <0x40001000 0x400>;
clocks = <&rcc STM32_CLOCK(APB1, 4)>,
<&rcc STM32_SRC_TIMPCLK1 NO_SEL>;
resets = <&rctl STM32_RESET(APB1, 4U)>;
resets = <&rctl STM32_RESET(APB1, 4)>;
interrupts = <17 0>;
interrupt-names = "global";
st,prescaler = <0>;
Expand All @@ -58,7 +58,7 @@
reg = <0x40014000 0x400>;
clocks = <&rcc STM32_CLOCK(APB2, 16)>,
<&rcc STM32_SRC_TIMPCLK1 NO_SEL>;
resets = <&rctl STM32_RESET(APB2, 16U)>;
resets = <&rctl STM32_RESET(APB2, 16)>;
interrupts = <20 0>;
interrupt-names = "global";
st,prescaler = <0>;
Expand Down
4 changes: 2 additions & 2 deletions dts/arm/st/f0/stm32f070.dtsi
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Original file line number Diff line number Diff line change
Expand Up @@ -14,7 +14,7 @@
compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40004400 0x400>;
clocks = <&rcc STM32_CLOCK(APB1, 17)>;
resets = <&rctl STM32_RESET(APB1, 17U)>;
resets = <&rctl STM32_RESET(APB1, 17)>;
interrupts = <28 0>;
status = "disabled";
};
Expand All @@ -24,7 +24,7 @@
reg = <0x40014000 0x400>;
clocks = <&rcc STM32_CLOCK(APB2, 16)>,
<&rcc STM32_SRC_TIMPCLK1 NO_SEL>;
resets = <&rctl STM32_RESET(APB2, 16U)>;
resets = <&rctl STM32_RESET(APB2, 16)>;
interrupts = <20 0>;
interrupt-names = "global";
st,prescaler = <0>;
Expand Down
8 changes: 4 additions & 4 deletions dts/arm/st/f0/stm32f070Xb.dtsi
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Original file line number Diff line number Diff line change
Expand Up @@ -29,7 +29,7 @@
compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40004800 0x400>;
clocks = <&rcc STM32_CLOCK(APB1, 18)>;
resets = <&rctl STM32_RESET(APB1, 18U)>;
resets = <&rctl STM32_RESET(APB1, 18)>;
interrupts = <29 0>;
status = "disabled";
};
Expand All @@ -38,7 +38,7 @@
compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40004c00 0x400>;
clocks = <&rcc STM32_CLOCK(APB1, 19)>;
resets = <&rctl STM32_RESET(APB1, 19U)>;
resets = <&rctl STM32_RESET(APB1, 19)>;
interrupts = <29 0>;
status = "disabled";
};
Expand Down Expand Up @@ -70,7 +70,7 @@
reg = <0x40001000 0x400>;
clocks = <&rcc STM32_CLOCK(APB1, 4)>,
<&rcc STM32_SRC_TIMPCLK1 NO_SEL>;
resets = <&rctl STM32_RESET(APB1, 4U)>;
resets = <&rctl STM32_RESET(APB1, 4)>;
interrupts = <17 0>;
interrupt-names = "global";
st,prescaler = <0>;
Expand All @@ -82,7 +82,7 @@
reg = <0x40001400 0x400>;
clocks = <&rcc STM32_CLOCK(APB1, 5)>,
<&rcc STM32_SRC_TIMPCLK1 NO_SEL>;
resets = <&rctl STM32_RESET(APB1, 5U)>;
resets = <&rctl STM32_RESET(APB1, 5)>;
interrupts = <18 0>;
interrupt-names = "global";
st,prescaler = <0>;
Expand Down
6 changes: 3 additions & 3 deletions dts/arm/st/f0/stm32f071.dtsi
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Original file line number Diff line number Diff line change
Expand Up @@ -45,7 +45,7 @@
compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40004800 0x400>;
clocks = <&rcc STM32_CLOCK(APB1, 18)>;
resets = <&rctl STM32_RESET(APB1, 18U)>;
resets = <&rctl STM32_RESET(APB1, 18)>;
interrupts = <29 0>;
status = "disabled";
};
Expand All @@ -54,7 +54,7 @@
compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40004c00 0x400>;
clocks = <&rcc STM32_CLOCK(APB1, 19)>;
resets = <&rctl STM32_RESET(APB1, 19U)>;
resets = <&rctl STM32_RESET(APB1, 19)>;
interrupts = <29 0>;
status = "disabled";
};
Expand All @@ -64,7 +64,7 @@
reg = <0x40001400 0x400>;
clocks = <&rcc STM32_CLOCK(APB1, 5)>,
<&rcc STM32_SRC_TIMPCLK1 NO_SEL>;
resets = <&rctl STM32_RESET(APB1, 5U)>;
resets = <&rctl STM32_RESET(APB1, 5)>;
interrupts = <18 0>;
interrupt-names = "global";
st,prescaler = <0>;
Expand Down
8 changes: 4 additions & 4 deletions dts/arm/st/f0/stm32f091.dtsi
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Original file line number Diff line number Diff line change
Expand Up @@ -20,7 +20,7 @@
compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40005000 0x400>;
clocks = <&rcc STM32_CLOCK(APB1, 20)>;
resets = <&rctl STM32_RESET(APB1, 20U)>;
resets = <&rctl STM32_RESET(APB1, 20)>;
interrupts = <29 0>;
status = "disabled";
};
Expand All @@ -29,7 +29,7 @@
compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40011400 0x400>;
clocks = <&rcc STM32_CLOCK(APB2, 5)>;
resets = <&rctl STM32_RESET(APB2, 5U)>;
resets = <&rctl STM32_RESET(APB2, 5)>;
interrupts = <29 0>;
status = "disabled";
};
Expand All @@ -38,7 +38,7 @@
compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40011800 0x400>;
clocks = <&rcc STM32_CLOCK(APB2, 6)>;
resets = <&rctl STM32_RESET(APB2, 6U)>;
resets = <&rctl STM32_RESET(APB2, 6)>;
interrupts = <29 0>;
status = "disabled";
};
Expand All @@ -47,7 +47,7 @@
compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40011c00 0x400>;
clocks = <&rcc STM32_CLOCK(APB2, 7)>;
resets = <&rctl STM32_RESET(APB2, 7U)>;
resets = <&rctl STM32_RESET(APB2, 7)>;
interrupts = <29 0>;
status = "disabled";
};
Expand Down
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