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boards: imx93_evk: Document imx-atf TRDC config for M33 DDR access #98757

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28 changes: 28 additions & 0 deletions boards/nxp/imx93_evk/doc/index.rst
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Expand Up @@ -338,6 +338,34 @@ to enable this, `imx-atf`_ can to be modified in "plat/imx/imx93/trdc_config.h".
.. _imx-atf:
https://github.com/nxp-imx/imx-atf

imx-atf changes:
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@iuliana-prodan iuliana-prodan Nov 3, 2025

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@RuoshanShi, does this change apply to real-time edge u-boot or simple (linux-nxp) u-boot?
Also, which Linux and U-Boot versions did you use for testing?

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@RuoshanShi RuoshanShi Nov 3, 2025 •
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@RuoshanShi, does this change apply to real-time edge u-boot or simple (linux-nxp) u-boot? Also, which Linux and U-Boot versions did you use for testing?

@iuliana-prodan I’m using the latest release of NXP’s file system. Since I’m working with the M33 core, I haven’t focused on the Linux system usage.
We need to make changes in the imx-atf repository and then compile it to generate bl31.bin. After that, copy bl31.bin to the imx-mkimg/iMX93 directory to build flash.bin. Then use uuu -b sd flash.bin to flash it onto the board.
In U-Boot, I use the following command to load the binary:
load mmc 1:1 0x84000000 zephyr.bin; dcache flush; bootaux 0x84000000 0
I noticed that the previous DDR target description only mentioned modifying plat/imx/imx93/trdc_config.h, so I added more detailed descriptions accordingly.


.. code-block:: console

git diff plat/imx/imx93/trdc_config.h
diff --git a/plat/imx/imx93/trdc_config.h b/plat/imx/imx93/trdc_config.h
index 6c8b8f8fa..b155f9048 100644
--- a/plat/imx/imx93/trdc_config.h
+++ b/plat/imx/imx93/trdc_config.h
@@ -302,7 +302,7 @@ struct trdc_mbc_config trdc_n_mbc[] = {
};

struct trdc_glbac_config trdc_n_mrc_glbac[] = {
- { 0, 0, SP(RW) | SU(RW) | NP(RW) | NU(RW) },
+ { 0, 0, SP(RWX) | SU(RW) | NP(RW) | NU(RW) },
{ 0, 1, SP(RWX) | SU(RWX) | NP(RWX) | NU(RWX) },
};

@@ -356,7 +356,7 @@ struct trdc_mrc_config trdc_n_mrc[] = {
struct trdc_mrc_config trdc_n_mrc[] = {
{ 0, 0, 0, 0x80000000, 0x80000000, 0, false }, /* MRC0 DRAM for S400 DID0 */
{ 0, 1, 0, 0x80000000, 0x80000000, 0, false }, /* MRC0 DRAM for MTR DID1 */
- { 0, 2, 0, 0x80000000, 0x80000000, 0, true }, /* MRC0 DRAM for M33 DID2 */
+ { 0, 2, 0, 0x80000000, 0x80000000, 1, true }, /* MRC0 DRAM for M33 DID2 */
{ 0, 3, 0, 0x80000000, 0x80000000, 1, false }, /* MRC0 DRAM for A55 DID3 */
{ 0, 5, 0, 0x80000000, 0x80000000, 0, false }, /* MRC0 DRAM for USDHC1 DID5 */
{ 0, 6, 0, 0x80000000, 0x80000000, 0, false }, /* MRC0 DRAM for USDHC2 DID6 */

Use this configuration to run basic Zephyr applications and kernel tests,
for example, with the :zephyr:code-sample:`synchronization` sample:

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