compiler_rt: Update x86 cpu model enums to LLVM 19

lib/compiler_rt/cpu_model/x86.zig

@@ -30,6 +30,7 @@ pub const Type = enum(u32) {
     intel_sierraforest,
     intel_grandridge,
     intel_clearwaterforest,
+    amdfam1ah,
 };
 pub const Subtype = enum(u32) {
     unknown,
@@ -67,6 +68,7 @@ pub const Subtype = enum(u32) {
     intel_corei7_arrowlake,
     intel_corei7_arrowlake_s,
     intel_corei7_pantherlake,
+    amdfam1ah_znver5,
 };
 pub const Feature = enum(u32) {
     cmov = 0,
@@ -93,8 +95,6 @@ pub const Feature = enum(u32) {
     avx512bw = 21,
     avx512dq = 22,
     avx512cd = 23,
-    avx512er = 24,
-    avx512pf = 25,
     avx512vbmi = 26,
     avx512ifma = 27,
     avx5124vnniw = 28,
@@ -107,10 +107,69 @@ pub const Feature = enum(u32) {
     avx512bitalg = 35,
     avx512bf16 = 36,
     avx512vp2intersect = 37,
+    adx = 40,
+    cldemote = 42,
+    clflushopt = 43,
+    clwb = 44,
+    clzero = 45,
+    cx16 = 46,
+    enqcmd = 48,
     f16c = 49,
+    fsgsbase = 50,
+    lwp = 56,
+    lzcnt = 57,
+    movbe = 58,
+    movdir64b = 59,
+    movdiri = 60,
+    mwaitx = 61,
+    pconfig = 63,
+    pku = 64,
+    prfchw = 66,
+    ptwrite = 67,
+    rdpid = 68,
+    rdrnd = 69,
+    rdseed = 70,
+    rtm = 71,
+    serialize = 72,
+    sgx = 73,
+    sha = 74,
+    shstk = 75,
+    tbm = 76,
+    tsxldtrk = 77,
+    vaes = 78,
+    waitpkg = 79,
+    wbnoinvd = 80,
+    xsave = 81,
+    xsavec = 82,
+    xsaveopt = 83,
+    xsaves = 84,
+    amx_tile = 85,
+    amx_int8 = 86,
+    amx_bf16 = 87,
+    uintr = 88,
+    hreset = 89,
+    kl = 90,
+    widekl = 92,
+    avxvnni = 93,
     avx512fp16 = 94,
+    avxifma = 99,
+    avxvnniint8 = 100,
+    avxneconvert = 101,
+    cmpccxadd = 102,
+    amx_fp16 = 103,
+    prefetchi = 104,
+    raoint = 105,
+    amx_complex = 106,
+    avxvnniint16 = 107,
+    sm3 = 108,
+    sha512 = 109,
+    sm4 = 110,
+    usermsr = 112,
+    avx10_1_256 = 113,
+    avx10_1_512 = 114,
     x86_64 = 95,
     x86_64_v2 = 96,
     x86_64_v3 = 97,
     x86_64_v4 = 98,
+    apxf = 111,
 };

lib/compiler_rt/x86_cpu_model.zig

@@ -165,6 +165,7 @@ comptime {
         .{ "x86_64_v2", {} },
         .{ "x86_64_v3", {} },
         .{ "x86_64_v4", {} },
+        .{ "apxf", {} },
     });
 
     var errors: []const u8 = "";
@@ -198,7 +199,7 @@ fn getAmdTypeAndSubtype(
     var s: Subtype = .unknown;
 
     switch (family) {
-        16 => {
+        16, 18 => {
             t = .amdfam10h;
             switch (model) {
                 2 => s = .amdfam10h_barcelona,
@@ -211,15 +212,9 @@ fn getAmdTypeAndSubtype(
         21 => {
             t = .amdfam15h;
             switch (model) {
-                0x60...0x7f, // 60h-7Fh: Excavator
-                => s = .amdfam15h_bdver4,
-
-                0x30...0x3f, // 30h-3Fh: Steamroller
-                => s = .amdfam15h_bdver3,
-
-                0x10...0x1f, // 10h-1Fh: Piledriver
-                => s = .amdfam15h_bdver2,
-
+                0x60...0x7f => s = .amdfam15h_bdver4, // 60h-7Fh: Excavator
+                0x30...0x3f => s = .amdfam15h_bdver3, // 30h-3Fh: Steamroller
+                0x10...0x1f => s = .amdfam15h_bdver2, // 10h-1Fh: Piledriver
                 0x00...0x0f => s = if (model == 0x02)
                     .amdfam15h_bdver2 // 02h: Piledriver
                 else
@@ -268,6 +263,12 @@ fn getAmdTypeAndSubtype(
                 else => {},
             }
         },
+        26 => {
+            t = .amdfam1ah;
+            if (model <= 0x77) { // Models 00h-77h
+                s = .amdfam1ah_znver5;
+            }
+        },
         else => {},
     }
 
@@ -338,15 +339,56 @@ fn getIntelTypeAndSubtype(
                 t = .intel_corei7;
                 s = .intel_corei7_tigerlake;
             },
-            0x97, 0x9a, 0xb7, 0xba, 0xbf, 0xaa, 0xac, 0xbe => {
+            0x97, 0x9a => {
                 t = .intel_corei7;
                 s = .intel_corei7_alderlake;
             },
+            // Raptorlake
+            0xb7, 0xba, 0xbf => {
+                t = .intel_corei7;
+                s = .intel_corei7_alderlake;
+            },
+            // Meteorlake
+            0xaa, 0xac => {
+                t = .intel_corei7;
+                s = .intel_corei7_alderlake;
+            },
+            // Gracemont
+            0xbe => {
+                t = .intel_corei7;
+                s = .intel_corei7_alderlake;
+            },
+            // Arrowlake and Arrowlake U
+            0xc5, 0xb5 => {
+                t = .intel_corei7;
+                s = .intel_corei7_arrowlake;
+            },
+            // Arrowlake S
+            0xc6 => {
+                t = .intel_corei7;
+                s = .intel_corei7_arrowlake_s;
+            },
+            // Lunarlake
+            0xbd => {
+                t = .intel_corei7;
+                s = .intel_corei7_arrowlake_s;
+            },
+            0xcc => {
+                t = .intel_corei7;
+                s = .intel_corei7_pantherlake;
+            },
+            // Icelake Xeon
             0x6a, 0x6c => {
                 t = .intel_corei7;
                 s = .intel_corei7_icelake_server;
             },
-            0xcf, 0x8f => {
+            // Emerald Rapids
+            0xcf => {
+                t = .intel_corei7;
+                s = .intel_corei7_sapphirerapids;
+            },
+            // Sapphire Rapids
+            0x8f => {
                 t = .intel_corei7;
                 s = .intel_corei7_sapphirerapids;
             },