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Slightly modernize compiler Verilog output #294

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wants to merge 3 commits into from
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Slightly modernize compiler Verilog output #294

wants to merge 3 commits into from

Commits on Feb 25, 2021

  1. fix(comp): nest translate_{on,off} for initial blocks 

    Synthesis tools like Yosys hate Synopsys pragmas, though they're
supported (it doesn't support simulation constructs anyway, which is
why.) It encourages `ifdef`s in order to handle this case, and always
defines `YOSYS` to help -- they're more flexible and explicit.

Currently for `initial` blocks in simulation that set initial register
values, we use `translate_off` pragma to have the synthesis tool ignore
things. But that block is already gated by `BSV_NO_INITIAL_BLOCKS` (so
you can simulate without bogus default register content). So we extend
that a bit.

By nesting the `translate_off` and `_on` pragmas *inside* of an `ifndef
YOSYS` clause (next to the `BSV_NO_INITIAL_BLOCKS` clause), Yosys will
ignore the synopsys pragmas, and issue no warning for them at all.

In the future, other tools or pragmas could be added to this chain,
though this really is a specific workaround for a specific tool, to some
extent.

Though this also makes the resulting code *look* better IMO, since it
scopes the pragma closer to its use site.

Signed-off-by: Austin Seipp <[email protected]>
    @thoughtpolice
    thoughtpolice committed Feb 25, 2021
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  2. fix(comp): use verilog attributes for {parallel, full}_case modifiers 

    Verilog 2001 attributes are supported by Vivado, Quartus, and other
tools (like Yosys) in order to parallel/full case semantics. Usage of
synopsys-specific synthesis comments can be done better this way, and it
suppresses a real warning with Yosys.

This takes us *out* of v95 territory, because Verilog attributes were
added in Verilog 2001. Currently, no fallback is supported, though this
could be fixed. It's unclear to me how much this harms "portability" of
the output Verilog code, but such features can always be added back
later on demand...

Signed-off-by: Austin Seipp <[email protected]>
    @thoughtpolice
    thoughtpolice committed Feb 25, 2021
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  3. fix(comp): use Verilog-2001 'always @*' combinational blocks 

    Signed-off-by: Austin Seipp <[email protected]>
    @thoughtpolice
    thoughtpolice committed Feb 25, 2021
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