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Slightly modernize compiler Verilog output #294

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Slightly modernize compiler Verilog output #294

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5f8bb7e
fix(comp): nest translate_{on,off} for initial blocks
thoughtpolice Mar 12, 2020
45b3593
fix(comp): use verilog attributes for {parallel, full}_case modifiers
thoughtpolice Mar 12, 2020
94da12c
fix(comp): use Verilog-2001 'always @*' combinational blocks
thoughtpolice Mar 25, 2020
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4 changes: 3 additions & 1 deletion src/comp/InlineReg.hs
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Original file line number Diff line number Diff line change
Expand Up @@ -176,7 +176,9 @@ mkInitialAssignments flags avis =
-- begin/end, even when there is only one item inside it
stmt = Vinitial $ VSeq $ map mkInit avis
in
[VMStmt { vi_translate_off = True, vi_body = stmt }]
-- The pretty printer automatically includes translate_off
-- pragmas for us.
[VMStmt { vi_translate_off = False, vi_body = stmt }]


-- make the conditional enable assignment to a register
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35 changes: 24 additions & 11 deletions src/comp/Verilog.hs
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Expand Up @@ -425,23 +425,31 @@ data VStmt


instance PPrint VStmt where
pPrint d p (VAt e s) = sep [text "@" <> pparen True (pPrint d 0 e), pPrint d 0 s]
pPrint d p (Valways (VAt e s)) = sep [text "always@" <> pparen True (pPrint d 0 e), pPrint d 0 s]
pPrint d p (Valways s) = sep [text "always", pPrint d 0 s]
pPrint d p (VAt e s)
| isEventCombinational e = sep [text "@*", pPrint d 0 s]
| otherwise = sep [text "@" <> pparen True (pPrint d 0 e), pPrint d 0 s]

pPrint d p (Valways s) = text "always" <+> pPrint d 0 s
pPrint d p (Vinitial s) =
-- NB: see https://github.com/B-Lang-org/bsc/issues/118 TL;DR
-- some tools like yosys hate synopsys pragmas, so gate them
-- *behind* the preprocessor block, so it will ignore them,
-- and not issue a warning.
text "`ifdef BSV_NO_INITIAL_BLOCKS" $$
text "`else // not BSV_NO_INITIAL_BLOCKS" $$
mkSynthPragma "translate_off" $$
sep [text "initial", pPrint d 0 s] $$
mkSynthPragma "translate_on" $$
text "`endif // BSV_NO_INITIAL_BLOCKS"
pPrint d p (VSeq ss) = text "begin" $+$ (text " " <> ppLines d ss) $+$ text "end"
pPrint d p s@(Vcasex {}) =
(text "casex" <+> pparen True (pPrint d 0 (vs_case_expr s))) <+>
pprintCaseAttributes (vs_parallel s) (vs_full s) $+$
pprintCaseAttributes (vs_parallel s) (vs_full s) <+>
(text "casex" <+> pparen True (pPrint d 0 (vs_case_expr s))) $+$
(text " " <> ppLines d (vs_case_arms s)) $+$
(text "endcase")
pPrint d p s@(Vcase {}) =
(text "case" <+> pparen True (pPrint d 0 (vs_case_expr s))) <+>
pprintCaseAttributes (vs_parallel s) (vs_full s) $+$
pprintCaseAttributes (vs_parallel s) (vs_full s) <+>
(text "case" <+> pparen True (pPrint d 0 (vs_case_expr s))) $+$
(text " " <> ppLines d (vs_case_arms s)) $+$
(text "endcase")
pPrint d p (VAssign v e) =
Expand Down Expand Up @@ -500,10 +508,9 @@ ppAs1 d i cs xs = text c1 <> ppAs1 d i c2 xs where

pprintCaseAttributes :: Bool -> Bool -> Doc
pprintCaseAttributes False False = empty
pprintCaseAttributes True False = mkSynthPragma "parallel_case"
pprintCaseAttributes False True = mkSynthPragma "full_case"
pprintCaseAttributes True True = mkSynthPragma "parallel_case full_case"

pprintCaseAttributes True False = text "(* parallel_case *)"
pprintCaseAttributes False True = text "(* full_case *)"
pprintCaseAttributes True True = text "(* parallel_case, full_case *)"

-- hack to check if expressions are known to be true or false
isOne :: VExpr -> Bool
Expand Down Expand Up @@ -664,6 +671,12 @@ instance PPrint VEventExpr where
pPrint d p (VEE e) = pPrint d p e
pPrint d p (VEEMacro s e) = text ("`" ++ s) <+> pPrint d (p+1) e

isEventCombinational :: VEventExpr -> Bool
isEventCombinational (VEEposedge _) = False
isEventCombinational (VEEnegedge _) = False
isEventCombinational (VEEMacro _ _) = False
isEventCombinational (VEE _) = True
isEventCombinational (VEEOr l r) = isEventCombinational l && isEventCombinational r

data VExpr
= VEConst Integer
Expand Down