RISC-V: Remove the CGetAddr instruction.

It was no longer needed after the removal of split register file
support and CHERI LLVM no longer emits it.  It remains in the ISA
quick reference summary table with a stub entry marking the encoding
as a removed instruction.

app-isaquick-riscv.tex

@@ -20,8 +20,6 @@ \chapter{CHERI-RISC-V ISA Quick Reference}
 		\mrnote{What is the RISC-V equivalent of CPtrCmp?}
 		\jwnote{Wouldn't the legacy comparisons do the trick? (described above)}
 
-		\mrnote{We need to add \insnriscvref{CGetAddr}}
-
 		\mrnote{Given that, unlike CHERI-MIPS, CHERI RISC-V does not yet
 		have a backwards-compatibility problem, we might take the opportunity
 		to rationalize the bit positions of permission bits.}
@@ -45,8 +43,6 @@ \chapter{CHERI-RISC-V ISA Quick Reference}
 
 		\rvcheriisaquick{CGetFlags}
 
-		\rvcheriisaquick{CGetAddr}
-
 		\rvcheriisaquick{CGetHigh}
 
 		\rvcheriisaquick{CGetTop}
@@ -847,10 +843,12 @@ \chapter{CHERI-RISC-V ISA Quick Reference}
 	\vspace{1em}
 
 	{\rvcherienctablefontsize
-	\def\rvcherireservedfootnotemark{$^\dagger$}
+	\def\rvcheriremovedfootnotemark{$^\dagger$}
+	\def\rvcherireservedfootnotemark{$^\ddagger$}
 	\rvcherienctablesrcdest\\\\
 	\footnotesize
-	$^\dagger$Reserved for future use.
+	$^\dagger$Previously used by a removed instruction.\\
+	$^\ddagger$Reserved for future use.
 	}
 
 	\vspace{1em}

app-versions-7-0-alpha1.tex

@@ -189,7 +189,7 @@
 Capability Branch if NULL (\insnnoref{CBEZ}) instructions have
 been added, which optimize pointer comparisons to NULL.
 
-\item A new Capability to Address (\insnref{CGetAddr})
+\item A new Capability to Address (\insnnoref{CGetAddr})
 instruction allows the direct retrieval of a capability's virtual address,
 rather than requiring the base and offset to be separately retrieved and added
 together.

app-versions-7-0-alpha4.tex

@@ -11,7 +11,7 @@
   These instructions cater better to a language mapping from C's
   \ccode{intptr_t} type to the virtual address, rather than offset, of a
   capability, which has been our focus previously.
-  These complement the previously added \insnref{CGetAddr} that allows
+  These complement the previously added \insnnoref{CGetAddr} that allows
   easier compiler access to a capability's virtual address.
 
 \item We have added two new experimental instructions, \insnref{CRAM}

chap-architecture.tex

@@ -608,21 +608,21 @@ \subsubsection{Address}
 \cbase{} and \coffset{} fields.
 The components of the virtual address may be accessed separately (e.g., via
 \insnref{CGetOffset}), or as a single combined entity (e.g., via
-\insnref{CGetAddr} and \insnref{CSetAddr}) depending on the software
+\insnref{CSetAddr}) depending on the software
 use case.
 For example, an integer cast of a C-language pointer might return either the
 offset or the virtual address, depending on the C-language interpretation
 being used.
 
-\note{As presently defined, CGetAddr and CGetOffset appear not to carry out
+\nwfnote{As presently defined, CGetOffset appears not to carry out
 bounds checks, which means that software really should get the length (and
 base) and do the math as well if the bound(s) matter(s).  Could there be
 utility to additional instructions for checked access when the intent is to
 extract only in-bound offsets and addresses?  Or, to dodge the question
 about what such a checked accessor returns when the cursor is out of bounds,
 a CBTS/CBTU-like pair of tests for the cursor being in-bounds?  While a
 CIncOffset by zero would clear the tag of an out of bounds capability, this
-seems too fragile, too prone to optimization, to depend on from C.}{nwf}
+seems too fragile, too prone to optimization, to depend on from C.}
 
 \subsubsection{Length}
 
@@ -1604,7 +1604,6 @@ \section{Capability-Aware Instructions}
 \item[Retrieve capability fields]
 These instructions extract specific capability-register fields and move their
 values into general-purpose (integer) registers:
-\insnref{CGetAddr},
 \insnref{CGetBase}, \insnref{CGetFlags}, \insnref{CGetLen},
 \insnref{CGetOffset}, \insnref{CGetPerm}, \insnref{CGetSealed},
 \insnref{CGetTag}, and \insnref{CGetType}.

chap-cheri-riscv.tex

@@ -1415,10 +1415,9 @@ \subsection{Separate Capability Register File}
   \insnriscvref{CClear} and \insnriscvref{FPClear} which cleared a set
   of general-purpose integer registers.
 
-\item A separate \insnref{CGetAddr} instruction to fetch the address
+\item A separate \insnnoref{CGetAddr} instruction to fetch the address
   of a capability register.  In a ``merged'' register file this can be
   obtained by reading the aliased general-purpose integer register.
-  Note that \insnref{CGetAddr} is currently still defined.
 
 \item A separate \insnnoref{CSub} instruction to compute the difference
   between addresses in two capability registers.  In a ``merged''

chap-cheri-x86-64.tex

@@ -659,9 +659,6 @@ \subsection{New CHERI Instructions}
 \subsubsection{Capability-Inspection Instructions}
 
 These instructions fetch a single field from a capability.
-Note that unlike CHERI-RISC-V, CHERI-x86-64 would not add a
-\insnref{CGetAddr} instruction since the \textbf{address} field of a
-capability can be obtained via a 64-bit \insnnoref{MOV} instruction.
 
 \begin{itemize}
   \item \insnxesref{GCPERM} - Get Capability Permissions

chap-isaref-riscv.tex

@@ -254,7 +254,6 @@ \section{CHERI-RISC-V Instructions}
 \input{insn-riscv/ccopytype}
 \input{insn-riscv/ccseal}
 \input{insn-riscv/cfromptr}
-\input{insn-riscv/cgetaddr}
 \input{insn-riscv/cgetbase}
 \input{insn-riscv/cgetflags}
 \input{insn-riscv/cgethigh}

chap-rationale.tex

@@ -1539,7 +1539,7 @@ \section{\DDC{} and \PCC{} Offsetting}
 CHERI no longer mandates \DDC{} and \PCC{} offsetting by default.
 CHERI architectures may provide it as an optional feature which can be
 enabled at runtime or may omit it entirely.  CHERI compilers always
-treat integer pointers as addresses using \insnref{CGetAddr} and
+treat integer pointers as addresses using
 \insnref{CSetAddr} to handle conversions between capabilities and
 integers.  The \insnref{CFromPtr} and \insnref{CToPtr} instructions
 may be provided on architectures supporting offsetting.

def-riscv-insns.tex

@@ -24,7 +24,7 @@
 \rvcherisrcdest[name=CGetSealed]{5}{rd}{cs1}
 \rvcherisrcdest[name=CGetOffset]{6}{rd}{cs1}
 \rvcherisrcdest[name=CGetFlags]{7}{rd}{cs1}
-\rvcherisrcdest[name=CGetAddr]{F}{rd}{cs1}
+\rvcherisrcdest[name=CGetAddr,noref,tablesuffix=\rvcheriremovedfootnotemark]{F}{rd}{cs1}
 \rvcherisrcdest[name=CGetTop]{18}{rd}{cs1}
 \rvcherisrcdest[name=CGetHigh]{17}{rd}{cs1}