HellaCache

HellaCacheModule.io = freechips.rocketchip.rocket.HellaCacheBundle{
  hartid = Input(UInt((1.W)))
  cpu = freechips.rocketchip.rocket.HellaCacheIO{
    req = chisel3.util.DecoupledIO{
      ready = Output(Bool())
      valid = Input(Bool())
      bits = freechips.rocketchip.rocket.HellaCacheReq{
        addr = Input(UInt((40.W)))
        tag = Input(UInt((7.W)))
        cmd = Input(UInt((5.W)))
        typ = Input(UInt((3.W)))
        phys = Input(Bool())
        data = Input(UInt((64.W)))
      }
    }
    s1_kill = Input(Bool())
    s1_data = freechips.rocketchip.rocket.HellaCacheWriteData{
      data = Input(UInt((64.W)))
      mask = Input(UInt((8.W)))
    }
    s2_nack = Output(Bool())
    s2_nack_cause_raw = Output(Bool())
    s2_kill = Input(Bool())
    resp = chisel3.util.Valid{
      valid = Output(Bool())
      bits = freechips.rocketchip.rocket.HellaCacheResp{
        addr = Output(UInt((40.W)))
        tag = Output(UInt((7.W)))
        cmd = Output(UInt((5.W)))
        typ = Output(UInt((3.W)))
        data = Output(UInt((64.W)))
        replay = Output(Bool())
        has_data = Output(Bool())
        data_word_bypass = Output(UInt((64.W)))
        data_raw = Output(UInt((64.W)))
        store_data = Output(UInt((64.W)))
      }
    }
    replay_next = Output(Bool())
    s2_xcpt = freechips.rocketchip.rocket.HellaCacheExceptions{
      ma = freechips.rocketchip.rocket.AlignmentExceptions{
        ld = Output(Bool())
        st = Output(Bool())
      }
      pf = freechips.rocketchip.rocket.AlignmentExceptions{
        ld = Output(Bool())
        st = Output(Bool())
      }
      ae = freechips.rocketchip.rocket.AlignmentExceptions{
        ld = Output(Bool())
        st = Output(Bool())
      }
    }
    ordered = Output(Bool())
    perf = freechips.rocketchip.rocket.HellaCachePerfEvents{
      acquire = Output(Bool())
      release = Output(Bool())
      grant = Output(Bool())
      tlbMiss = Output(Bool())
      blocked = Output(Bool())
    }
    keep_clock_enabled = Input(Bool())
    clock_enabled = Output(Bool())
  }
  ptw = freechips.rocketchip.rocket.TLBPTWIO{
    req = chisel3.util.DecoupledIO{
      ready = Input(Bool())
      valid = Output(Bool())
      bits = chisel3.util.Valid{
        valid = Output(Bool())
        bits = freechips.rocketchip.rocket.PTWReq{
          addr = Output(UInt((27.W)))
        }
      }
    }
    resp = chisel3.util.Valid{
      valid = Input(Bool())
      bits = freechips.rocketchip.rocket.PTWResp{
        ae = Input(Bool())
        pte = freechips.rocketchip.rocket.PTE{
          ppn = Input(UInt((54.W)))
          reserved_for_software = Input(UInt((2.W)))
          d = Input(Bool())
          a = Input(Bool())
          g = Input(Bool())
          u = Input(Bool())
          x = Input(Bool())
          w = Input(Bool())
          r = Input(Bool())
          v = Input(Bool())
        }
        level = Input(UInt((2.W)))
        fragmented_superpage = Input(Bool())
        homogeneous = Input(Bool())
      }
    }
    ptbr = freechips.rocketchip.rocket.PTBR{
      mode = Input(UInt((4.W)))
      asid = Input(UInt((16.W)))
      ppn = Input(UInt((44.W)))
    }
    status = freechips.rocketchip.rocket.MStatus{
      debug = Input(Bool())
      isa = Input(UInt((32.W)))
      dprv = Input(UInt((2.W)))
      prv = Input(UInt((2.W)))
      sd = Input(Bool())
      zero2 = Input(UInt((27.W)))
      sxl = Input(UInt((2.W)))
      uxl = Input(UInt((2.W)))
      sd_rv32 = Input(Bool())
      zero1 = Input(UInt((8.W)))
      tsr = Input(Bool())
      tw = Input(Bool())
      tvm = Input(Bool())
      mxr = Input(Bool())
      sum = Input(Bool())
      mprv = Input(Bool())
      xs = Input(UInt((2.W)))
      fs = Input(UInt((2.W)))
      mpp = Input(UInt((2.W)))
      hpp = Input(UInt((2.W)))
      spp = Input(UInt((1.W)))
      mpie = Input(Bool())
      hpie = Input(Bool())
      spie = Input(Bool())
      upie = Input(Bool())
      mie = Input(Bool())
      hie = Input(Bool())
      sie = Input(Bool())
      uie = Input(Bool())
    }
    pmp = Vec(
      freechips.rocketchip.rocket.PMP{
        cfg = freechips.rocketchip.rocket.PMPConfig{
          l = Input(Bool())
          res = Input(UInt((2.W)))
          a = Input(UInt((2.W)))
          x = Input(Bool())
          w = Input(Bool())
          r = Input(Bool())
        }
        addr = Input(UInt((36.W)))
        mask = Input(UInt((38.W)))
      },
      freechips.rocketchip.rocket.PMP{
        cfg = freechips.rocketchip.rocket.PMPConfig{
          l = Input(Bool())
          res = Input(UInt((2.W)))
          a = Input(UInt((2.W)))
          x = Input(Bool())
          w = Input(Bool())
          r = Input(Bool())
        }
        addr = Input(UInt((36.W)))
        mask = Input(UInt((38.W)))
      },
      freechips.rocketchip.rocket.PMP{
        cfg = freechips.rocketchip.rocket.PMPConfig{
          l = Input(Bool())
          res = Input(UInt((2.W)))
          a = Input(UInt((2.W)))
          x = Input(Bool())
          w = Input(Bool())
          r = Input(Bool())
        }
        addr = Input(UInt((36.W)))
        mask = Input(UInt((38.W)))
      },
      freechips.rocketchip.rocket.PMP{
        cfg = freechips.rocketchip.rocket.PMPConfig{
          l = Input(Bool())
          res = Input(UInt((2.W)))
          a = Input(UInt((2.W)))
          x = Input(Bool())
          w = Input(Bool())
          r = Input(Bool())
        }
        addr = Input(UInt((36.W)))
        mask = Input(UInt((38.W)))
      },
      freechips.rocketchip.rocket.PMP{
        cfg = freechips.rocketchip.rocket.PMPConfig{
          l = Input(Bool())
          res = Input(UInt((2.W)))
          a = Input(UInt((2.W)))
          x = Input(Bool())
          w = Input(Bool())
          r = Input(Bool())
        }
        addr = Input(UInt((36.W)))
        mask = Input(UInt((38.W)))
      },
      freechips.rocketchip.rocket.PMP{
        cfg = freechips.rocketchip.rocket.PMPConfig{
          l = Input(Bool())
          res = Input(UInt((2.W)))
          a = Input(UInt((2.W)))
          x = Input(Bool())
          w = Input(Bool())
          r = Input(Bool())
        }
        addr = Input(UInt((36.W)))
        mask = Input(UInt((38.W)))
      },
      freechips.rocketchip.rocket.PMP{
        cfg = freechips.rocketchip.rocket.PMPConfig{
          l = Input(Bool())
          res = Input(UInt((2.W)))
          a = Input(UInt((2.W)))
          x = Input(Bool())
          w = Input(Bool())
          r = Input(Bool())
        }
        addr = Input(UInt((36.W)))
        mask = Input(UInt((38.W)))
      },
      freechips.rocketchip.rocket.PMP{
        cfg = freechips.rocketchip.rocket.PMPConfig{
          l = Input(Bool())
          res = Input(UInt((2.W)))
          a = Input(UInt((2.W)))
          x = Input(Bool())
          w = Input(Bool())
          r = Input(Bool())
        }
        addr = Input(UInt((36.W)))
        mask = Input(UInt((38.W)))
      },
    )
    customCSRs = freechips.rocketchip.rocket.RocketCustomCSRs{
      csrs = Vec(
        freechips.rocketchip.tile.CustomCSRIO{
          wen = Input(Bool())
          wdata = Input(UInt((64.W)))
          value = Input(UInt((64.W)))
        },
        freechips.rocketchip.tile.CustomCSRIO{
          wen = Input(Bool())
          wdata = Input(UInt((64.W)))
          value = Input(UInt((64.W)))
        },
        freechips.rocketchip.tile.CustomCSRIO{
          wen = Input(Bool())
          wdata = Input(UInt((64.W)))
          value = Input(UInt((64.W)))
        },
        freechips.rocketchip.tile.CustomCSRIO{
          wen = Input(Bool())
          wdata = Input(UInt((64.W)))
          value = Input(UInt((64.W)))
        },
      )
    }
  }
  errors = freechips.rocketchip.rocket.DCacheErrors{
    bus = chisel3.util.Valid{
      valid = Output(Bool())
      bits = Output(UInt((38.W)))
    }
  }
}
HellaCacheModule.tl_out = freechips.rocketchip.tilelink.TLBundle{
  a = chisel3.util.DecoupledIO{
    ready = Input(Bool())
    valid = Output(Bool())
    bits = freechips.rocketchip.tilelink.TLBundleA{
      opcode = Output(UInt((3.W)))
      param = Output(UInt((3.W)))
      size = Output(UInt((3.W)))
      source = Output(UInt((1.W)))
      address = Output(UInt((38.W)))
      mask = Output(UInt((8.W)))
      data = Output(UInt((64.W)))
      corrupt = Output(Bool())
    }
  }
  b = chisel3.util.DecoupledIO{
    ready = Output(Bool())
    valid = Input(Bool())
    bits = freechips.rocketchip.tilelink.TLBundleB{
      opcode = Input(UInt((3.W)))
      param = Input(UInt((2.W)))
      size = Input(UInt((3.W)))
      source = Input(UInt((1.W)))
      address = Input(UInt((38.W)))
      mask = Input(UInt((8.W)))
      data = Input(UInt((64.W)))
      corrupt = Input(Bool())
    }
  }
  c = chisel3.util.DecoupledIO{
    ready = Input(Bool())
    valid = Output(Bool())
    bits = freechips.rocketchip.tilelink.TLBundleC{
      opcode = Output(UInt((3.W)))
      param = Output(UInt((3.W)))
      size = Output(UInt((3.W)))
      source = Output(UInt((1.W)))
      address = Output(UInt((38.W)))
      data = Output(UInt((64.W)))
      corrupt = Output(Bool())
    }
  }
  d = chisel3.util.DecoupledIO{
    ready = Output(Bool())
    valid = Input(Bool())
    bits = freechips.rocketchip.tilelink.TLBundleD{
      opcode = Input(UInt((3.W)))
      param = Input(UInt((2.W)))
      size = Input(UInt((3.W)))
      source = Input(UInt((1.W)))
      sink = Input(UInt((3.W)))
      denied = Input(Bool())
      data = Input(UInt((64.W)))
      corrupt = Input(Bool())
    }
  }
  e = chisel3.util.DecoupledIO{
    ready = Input(Bool())
    valid = Output(Bool())
    bits = freechips.rocketchip.tilelink.TLBundleE{
      sink = Output(UInt((3.W)))
    }
  }
}