ICache

what's going on with the scratchpad???

• seems to be off in the default config; used in tiny

how is cache invalidated

• FENCE.I instruction (risc-v spec page 31)
• in rocket whole cache is invalidated
• can't invalidate icache of other harts
• might change in future

structure

• lfsr used to determine way to replace on refill

arrays

tag_array

• sram
• stores part of paddr not used to index cache
• read in cycle 0

vb_array

• register
• stores if cache line is valid (1 bit)
• read in cycle 1

data_arrays

• store cache lines
• multiple arrays if tilelink width > addrwidth
• 1 big array for all ways
• read in cycle 0

tlb

• tlb is located in Frontend

IO

• io for a BigCore

ICacheModule.io = freechips.rocketchip.rocket.ICacheBundle{
  hartid = Input(UInt((1.W)))                            // id of the thread/processor
  req = chisel3.util.DecoupledIO{                        // read request
    ready = Output(Bool())                               // true if tl data on d is not arriving
    valid = Input(Bool())
    bits = freechips.rocketchip.rocket.ICacheReq{
      addr = Input(UInt((39.W)))
    }
  }
  s1_paddr = Input(UInt((38.W)))                         // physical address delayed one cycle w.r.t. req
  s2_vaddr = Input(UInt((39.W)))                         // virtual address delayed two cycles w.r.t. req - 1 bit more 
  s1_kill = Input(Bool())
  s2_kill = Input(Bool())
  s2_prefetch = Input(Bool())
  resp = chisel3.util.Valid{                             // read response
    valid = Output(Bool())
    bits = freechips.rocketchip.rocket.ICacheResp{
      data = Output(UInt((32.W)))
      replay = Output(Bool())                            // seems to indicate that the instruction is not valid?? (e.g. data ecc error)
      ae = Output(Bool())                                // tag ecc error
    }
  }
  invalidate = Input(Bool())
  errors = freechips.rocketchip.rocket.ICacheErrors{
  }
  perf = freechips.rocketchip.rocket.ICachePerfEvents{
    acquire = Output(Bool())
  }
  clock_enabled = Input(Bool())
  keep_clock_enabled = Output(Bool())
}

//tilelink master port
ICacheModule.tl_out = freechips.rocketchip.tilelink.TLBundle{
  a = chisel3.util.DecoupledIO{
    ready = Input(Bool())
    valid = Output(Bool())
    bits = freechips.rocketchip.tilelink.TLBundleA{
      opcode = Output(UInt((3.W)))
      param = Output(UInt((3.W)))
      size = Output(UInt((3.W)))
      source = Output(UInt((1.W)))
      address = Output(UInt((38.W)))
      mask = Output(UInt((8.W)))
      data = Output(UInt((64.W)))
      corrupt = Output(Bool())
    }
  }
  b = chisel3.util.DecoupledIO{
    ready = Output(Bool())
    valid = Input(Bool())
    bits = freechips.rocketchip.tilelink.TLBundleB{
      opcode = Input(UInt((3.W)))
      param = Input(UInt((2.W)))
      size = Input(UInt((3.W)))
      source = Input(UInt((1.W)))
      address = Input(UInt((38.W)))
      mask = Input(UInt((8.W)))
      data = Input(UInt((64.W)))
      corrupt = Input(Bool())
    }
  }
  c = chisel3.util.DecoupledIO{
    ready = Input(Bool())
    valid = Output(Bool())
    bits = freechips.rocketchip.tilelink.TLBundleC{
      opcode = Output(UInt((3.W)))
      param = Output(UInt((3.W)))
      size = Output(UInt((3.W)))
      source = Output(UInt((1.W)))
      address = Output(UInt((38.W)))
      data = Output(UInt((64.W)))
      corrupt = Output(Bool())
    }
  }
  d = chisel3.util.DecoupledIO{
    ready = Output(Bool())
    valid = Input(Bool())
    bits = freechips.rocketchip.tilelink.TLBundleD{
      opcode = Input(UInt((3.W)))
      param = Input(UInt((2.W)))
      size = Input(UInt((3.W)))
      source = Input(UInt((1.W)))
      sink = Input(UInt((3.W)))
      denied = Input(Bool())
      data = Input(UInt((64.W)))
      corrupt = Input(Bool())
    }
  }
  e = chisel3.util.DecoupledIO{
    ready = Input(Bool())
    valid = Output(Bool())
    bits = freechips.rocketchip.tilelink.TLBundleE{
      sink = Output(UInt((3.W)))
    }
  }
}

ICacheModule.tl_in = doesn't exist (None) => no slave port (used only in scrtchpad cofig)