AP_HAL_ChibiOS: move to using Instruction RAM with External Flash setup

Icatme · Sep 1, 2021 · 81dc237 · 81dc237
1 parent 1eb318c
commit 81dc237
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Showing 3 changed files with 40 additions and 13 deletions.
diff --git a/libraries/AP_HAL_ChibiOS/hwdef/common/common_extf.ld b/libraries/AP_HAL_ChibiOS/hwdef/common/common_extf.ld
@@ -40,6 +40,10 @@ __ram0_start__          = ORIGIN(ram0);
 __ram0_size__           = LENGTH(ram0);
 __ram0_end__            = __ram0_start__ + __ram0_size__;
 
+__instram_start__      = ORIGIN(instram);
+__instram_size__       = LENGTH(instram);
+__instram_end__        = __instram_start__ + __instram_size__;
+
 ENTRY(Reset_Handler)
 
 SECTIONS
@@ -50,28 +54,42 @@ SECTIONS
     startup : ALIGN(16) SUBALIGN(16)
     {
         KEEP(*(.vectors))
-    } > irq_flash
+    } > default_flash
 
     constructors : ALIGN(4) SUBALIGN(4)
     {
         __init_array_base__ = .;
         KEEP(*(SORT(.init_array.*)))
         KEEP(*(.init_array))
         __init_array_end__ = .;
-    } > irq_flash
+    } > default_flash
 
     destructors : ALIGN(4) SUBALIGN(4)
     {
         __fini_array_base__ = .;
         KEEP(*(.fini_array))
         KEEP(*(SORT(.fini_array.*)))
         __fini_array_end__ = .;
-    } > irq_flash
+    } > default_flash
+
+    .ramfunc : ALIGN(4) SUBALIGN(4)
+    {
+        . = ALIGN(4);
+        __instram_init_text__ = LOADADDR(.ramfunc);
+        __instram_init__ = .;
+        EXCLUDE_FILE (*vectors.o *crt0_v7m.o *crt1.o)
+        *libch.a:*(.text .text.* .rodata .rodata.* .glue_7t .glue_7 .gcc*)
+        *(.ramfunc)
+        . = ALIGN(4);
+        __instram_end__ = .;
+    } > instram AT > default_flash
 
     .text : ALIGN(4) SUBALIGN(4)
     {
         /* we want app_descriptor near the start of flash so a false
            positive isn't found by the bootloader (eg. ROMFS) */
+        KEEP(*libch.a:vectors.o);
+        KEEP(*libch.a:crt0_v7m.o);
         KEEP(*(.app_descriptor));
         *(.text)
         *(.text.*)
@@ -82,11 +100,6 @@ SECTIONS
         *(.gcc*)
     } > default_flash
 
-    .irq : ALIGN(4) SUBALIGN(4)
-    {
-        *(.irq)
-    } > irq_flash
-
     .ARM.extab :
     {
         *(.ARM.extab* .gnu.linkonce.armextab.*)

diff --git a/libraries/AP_HAL_ChibiOS/hwdef/scripts/STM32H757xx.py b/libraries/AP_HAL_ChibiOS/hwdef/scripts/STM32H757xx.py
@@ -23,9 +23,10 @@
         (0x20000000, 128, 2), # DTCM, tightly coupled, no DMA, fast
         (0x38000000,  64, 1), # SRAM4. This supports both DMA and BDMA ops
         (0x24000000, 512, 4), # AXI SRAM. Use this for SDMMC IDMA ops
-        (0x00000400,  63, 2), # ITCM (first 1k removed, to keep address 0 unused)
     ],
 
+    'INSTRUCTION_RAM' : (0x00000400, 63), # ITCM (first 1k removed, to keep address 0 unused)
+
     'EXPECTED_CLOCK' : 400000000,
 
     # this MCU has M7 instructions and hardware double precision

diff --git a/libraries/AP_HAL_ChibiOS/hwdef/scripts/chibios_hwdef.py b/libraries/AP_HAL_ChibiOS/hwdef/scripts/chibios_hwdef.py
@@ -771,12 +771,21 @@ def write_mcu_config(f):
     f.write('#define EXTERNAL_PROG_FLASH_MB %u\n' % get_config('EXTERNAL_PROG_FLASH_MB', default=0, type=int))
 
     env_vars['EXTERNAL_PROG_FLASH_MB'] = get_config('EXTERNAL_PROG_FLASH_MB', default=0, type=int)
+
+    if env_vars['EXTERNAL_PROG_FLASH_MB'] and not args.bootloader:
+        f.write('#define CRT1_RAMFUNC_ENABLE TRUE\n') # this will enable loading program sections to RAM
+        f.write('#define __RAMFUNC__ __attribute__ ((long_call, __section__(".ramfunc")))\n')
+        f.write('#define PORT_IRQ_ATTRIBUTES __RAMFUNC__')
+    else:
+        f.write('#define CRT1_RAMFUNC_ENABLE FALSE\n')
+
     if args.bootloader:
+        if env_vars['EXTERNAL_PROG_FLASH_MB']:
+            f.write('#define APP_START_ADDRESS 0x90000000\n')
+            f.write('#define BOOT_FROM_EXT_FLASH 1\n')
         f.write('#define FLASH_BOOTLOADER_LOAD_KB %u\n' % get_config('FLASH_BOOTLOADER_LOAD_KB', type=int))
         f.write('#define FLASH_RESERVE_END_KB %u\n' % get_config('FLASH_RESERVE_END_KB', default=0, type=int))
         f.write('#define APP_START_OFFSET_KB %u\n' % get_config('APP_START_OFFSET_KB', default=0, type=int))
-    else:
-        f.write('#define PORT_IRQ_ATTRIBUTES __attribute__((section(".irq")))')
     f.write('\n')
 
     ram_map = get_mcu_config('RAM_MAP', True)
@@ -922,9 +931,13 @@ def write_ldscript(fname):
 
     # ram layout
     ram_map = get_mcu_config('RAM_MAP', True)
+    instruction_ram = get_mcu_config('INSTRUCTION_RAM', False)
 
     flash_base = 0x08000000 + flash_reserve_start * 1024
     ext_flash_base = 0x90000000
+    if instruction_ram is not None:
+        instruction_ram_base = instruction_ram[0]
+        instruction_ram_length = instruction_ram[1]
 
     if not args.bootloader:
         flash_length = flash_size - (flash_reserve_start + flash_reserve_end)
@@ -962,13 +975,13 @@ def write_ldscript(fname):
 MEMORY
 {
     default_flash : org = 0x%08x, len = %uM
-    irq_flash : org = 0x%08x, len = %uK
+    instram : org = 0x%08x, len = %uK
     ram0  : org = 0x%08x, len = %u
 }
 
 INCLUDE common_extf.ld
 ''' % (ext_flash_base, ext_flash_length,
-       flash_base, flash_length,
+       instruction_ram_base, instruction_ram_length,
        ram0_start, ram0_len))
 
 def copy_common_linkerscript(outdir, hwdef):