TX project about hardware acceleration performance of a Xilinx Zynq-7000 SoC ZC702 using image processing functions
In this report and associated Vivado source code, we try to evaluate the hardware acceleration performance of the Xilinx Zynq-7000 SoC ZC702 using image processing functions in C++, synthesised into HDL block IP with Vivado HLS and implemented on an ARM+FPGA interconnected architecture.
See also the list of contributors who participated in this project.
This project is licensed under the GNU General Public License v3.0 - see the LICENSE.md file for details.