You signed in with another tab or window. Reload to refresh your session.You signed out in another tab or window. Reload to refresh your session.You switched accounts on another tab or window. Reload to refresh your session.Dismiss alert
This file contains hidden or bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
This PR contains several changes for debugging TDM operation
It is observed that when keepalive watchdog is disabled, the operation of TDM is smooth and does not hang. Maybe some change is needed to create the thread
Currently undergoing long run streaming testing to check for hangs
There are glitches that are observed at the LA analyzer, but do not happen on the board. It is observed that the LA occasionally skips a clock cycle, causing the data to mismatch with the board by 1 bit.
However this does not mean that the data is corrupted!
==============
There are several important steps to take note to ensure correct signal observation
The following setting should be used:
Scope setting: 500MS / 1.8V+ <-- It is observed that 3.3V has higher chance of 1bit error at the scope, it does not affect the board data.
Analyzer setting:
If possible, power down the board fully to reset the sensor as well. This will yield results that are easier to compare scope vs UART data
Because 8CH is used there will be 2 DMA buffers combined to produce final requested bytes
So half the size of each buffer should be requested.
Also, FIFO is reset upon each transfer completion to avoid stale bytes in the FIFO that may be copied into DMA buffer
Use of delayms/us will cause the CPU to busy wait, switch to using usleep APIs which will yield the CPU. This fixes TASH getting stuck as well every ~7s
It was also observed that when the keepalive watchdog is disabled, the data can be constantly streamed with no sudden stoppage or hang
bitclock error is reported by the software decoder, not the chip. If the decoder skips 1 clock, the frame display is wrong, but the the chip is receiving the data fine. I have asked eric to pass you the sample exported data and the log output after 12 hours to compare
bitclock error is reported by the software decoder, not the chip. If the decoder skips 1 clock, the frame display is wrong, but the the chip is receiving the data fine. I have asked eric to pass you the sample exported data and the log output after 12 hours to compare
FSYNC has very short contained CH1CH5 , missing three samples from CH6Ch8
. I want to see full reading operation * please tell me "Why BCLK is stopped?"
can you explain about GDMA operation with TDM ?
. High Level Working Flow diagram
. Multi Block Transfer ( link structure , the condition of DMA Interrupt )
. relation between TDM FIFO to GDMA Memory
Add this suggestion to a batch that can be applied as a single commit.This suggestion is invalid because no changes were made to the code.Suggestions cannot be applied while the pull request is closed.Suggestions cannot be applied while viewing a subset of changes.Only one suggestion per line can be applied in a batch.Add this suggestion to a batch that can be applied as a single commit.Applying suggestions on deleted lines is not supported.You must change the existing code in this line in order to create a valid suggestion.Outdated suggestions cannot be applied.This suggestion has been applied or marked resolved.Suggestions cannot be applied from pending reviews.Suggestions cannot be applied on multi-line comments.Suggestions cannot be applied while the pull request is queued to merge.Suggestion cannot be applied right now. Please check back later.
This PR contains several changes for debugging TDM operation
It is observed that when keepalive watchdog is disabled, the operation of TDM is smooth and does not hang. Maybe some change is needed to create the thread
Currently undergoing long run streaming testing to check for hangs
There are glitches that are observed at the LA analyzer, but do not happen on the board. It is observed that the LA occasionally skips a clock cycle, causing the data to mismatch with the board by 1 bit.
However this does not mean that the data is corrupted!
==============
There are several important steps to take note to ensure correct signal observation
Please update the TDM analyzer plugin @ https://github.com/bitswype/saleae_tdm_analyer/releases to latest
The following setting should be used:
Scope setting: 500MS / 1.8V+ <-- It is observed that 3.3V has higher chance of 1bit error at the scope, it does not affect the board data.
Analyzer setting:
