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feat(smp): enable multi-core startup and basic shell support for all archs#12

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li041 wants to merge 1 commit intoStarry-OS:mainfrom
li041:smp
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feat(smp): enable multi-core startup and basic shell support for all archs#12
li041 wants to merge 1 commit intoStarry-OS:mainfrom
li041:smp

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@li041
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@li041 li041 commented Nov 10, 2025

Implements SMP initialization to start secondary CPUs during kernel boot.
Each secondary CPU runs its own runtime initialization and joins the scheduler, enabling parallel execution of tasks and improved CPU utilization.

Comment on lines +249 to +253
#[cfg(target_arch = "riscv64")]
unsafe {
use riscv::register::sstatus;
sstatus::set_sum();
}
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I believe this part should be moved into https://github.com/Starry-OS/axcpu/blob/main/src/riscv/init.rs. You may take a look at Starry-OS/axcpu#8, where they also encountered a similar issue to enable user memory access in supervisor.

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I see, I will modify it later.

Comment on lines +54 to +61
#[cfg(target_arch = "riscv64")]
{
use riscv::register::sstatus;
unsafe {
sstatus::set_sum();
}
}

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Same here.

@AsakuraMizu
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This mitigation does not work for any other RISC-V platform other than QEMU Virt. It does not even compile. We need a better solution.

@AsakuraMizu
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I still insist on moving whole https://github.com/Starry-OS/arceos/blob/main/modules/axhal/src/percpu.rs into axcpu.

@li041
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li041 commented Nov 10, 2025

I still insist on moving whole https://github.com/Starry-OS/arceos/blob/main/modules/axhal/src/percpu.rs into axcpu.

I don’t think the semantics of percpu really fit the design of the axcpu crate. The axcpu crate provides privileged instruction and structure abstractions for various CPU ARCH. But percpu concentrate more on cpu and task abstraction.

@AsakuraMizu
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I don’t think the semantics of percpu really fit the design of the axcpu crate. The axcpu crate provides privileged instruction and structure abstractions for various CPU ARCH. But percpu concentrate more on cpu and task abstraction.

Okay, I'm convinced. I'll think about it some more. But the current design is definitely not very good.

}
#[cfg(all(feature = "irq", target_arch = "riscv64"))]
{
axplat_riscv64_qemu_virt::register_this_cpu_id(this_cpu_id);
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I wonder if it’s essential on other riscv64 plat? I mean directly use axplat_riscv64_qemu_virt api here,it only works on this platform?

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Yeah, I feel sorry that I didn't consider other riscv64 plat right now.

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platforms/axplat-riscv64-qemu-virt/src/init.rs
maybe it should put here

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@AsakuraMizu AsakuraMizu Nov 10, 2025

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platforms/axplat-riscv64-qemu-virt/src/init.rs maybe it should put here

That falls back to the same problem. The fundamental issue is that there's currently no way to obtain the CPU ID in axplat.

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? PlatinitIf has cpu_id param? Doesn’t it?

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? PlatinitIf has cpu_id param? Doesn’t it?

I apologize for the inaccuracy in my statement. The exact issue is that there's currently no way to obtain the hart ID at https://github.com/Starry-OS/axplat_crates/blob/main/platforms/axplat-riscv64-qemu-virt/src/irq.rs#L192.

@AsakuraMizu
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AsakuraMizu commented Nov 10, 2025

What if we move some parts of percpu.rs (CPU_ID/IS_BSP and related functions) into axplat crate?

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