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feat(smp): enable multi-core startup and basic shell support for all archs #12

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feat(smp): enable multi-core startup and basic shell support for all archs #12

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8 changes: 8 additions & 0 deletions modules/axhal/src/percpu.rs
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Expand Up @@ -80,6 +80,10 @@ pub(crate) fn init_primary(cpu_id: usize) {
CPU_ID.write_current_raw(cpu_id);
IS_BSP.write_current_raw(true);
}
#[cfg(all(feature = "irq", target_arch = "riscv64"))]
{
axplat_riscv64_qemu_virt::register_this_cpu_id(this_cpu_id);
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@guoweikang guoweikang Nov 10, 2025

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I wonder if it’s essential on other riscv64 plat? I mean directly use axplat_riscv64_qemu_virt api here,it only works on this platform?

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@li041 li041 Nov 10, 2025

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Yeah, I feel sorry that I didn't consider other riscv64 plat right now.

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@guoweikang guoweikang Nov 10, 2025

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platforms/axplat-riscv64-qemu-virt/src/init.rs
maybe it should put here

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@AsakuraMizu AsakuraMizu Nov 10, 2025 •
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platforms/axplat-riscv64-qemu-virt/src/init.rs maybe it should put here

That falls back to the same problem. The fundamental issue is that there's currently no way to obtain the CPU ID in axplat.

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@guoweikang guoweikang Nov 10, 2025

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? PlatinitIf has cpu_id param? Doesn’t it?

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@AsakuraMizu AsakuraMizu Nov 10, 2025

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? PlatinitIf has cpu_id param? Doesn’t it?

I apologize for the inaccuracy in my statement. The exact issue is that there's currently no way to obtain the hart ID at https://github.com/Starry-OS/axplat_crates/blob/main/platforms/axplat-riscv64-qemu-virt/src/irq.rs#L192.

}
}

#[allow(dead_code)]
Expand All @@ -89,4 +93,8 @@ pub(crate) fn init_secondary(cpu_id: usize) {
CPU_ID.write_current_raw(cpu_id);
IS_BSP.write_current_raw(false);
}
#[cfg(all(feature = "irq", target_arch = "riscv64"))]
{
axplat_riscv64_qemu_virt::register_this_cpu_id(this_cpu_id);
}
}
3 changes: 3 additions & 0 deletions modules/axruntime/Cargo.toml
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Expand Up @@ -48,3 +48,6 @@ chrono = { workspace = true, optional = true }
crate_interface = { workspace = true }
indoc = "2"
percpu = { workspace = true, optional = true }

[target.'cfg(any(target_arch = "riscv32", target_arch = "riscv64"))'.dependencies]
riscv = "0.14"
5 changes: 5 additions & 0 deletions modules/axruntime/src/lib.rs
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Expand Up @@ -246,6 +246,11 @@ pub fn rust_main(cpu_id: usize, arg: usize) -> ! {
core::hint::spin_loop();
}

#[cfg(target_arch = "riscv64")]
unsafe {
use riscv::register::sstatus;
sstatus::set_sum();
}
Comment on lines +249 to +253
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@AsakuraMizu AsakuraMizu Nov 10, 2025

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I believe this part should be moved into https://github.com/Starry-OS/axcpu/blob/main/src/riscv/init.rs. You may take a look at Starry-OS/axcpu#8, where they also encountered a similar issue to enable user memory access in supervisor.

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@li041 li041 Nov 10, 2025

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I see, I will modify it later.

unsafe { main() };

#[cfg(feature = "multitask")]
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8 changes: 8 additions & 0 deletions modules/axruntime/src/mp.rs
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Expand Up @@ -51,6 +51,14 @@ pub fn rust_main_secondary(cpu_id: usize) -> ! {
#[cfg(feature = "ipi")]
axipi::init();

#[cfg(target_arch = "riscv64")]
{
use riscv::register::sstatus;
unsafe {
sstatus::set_sum();
}
}

Comment on lines +54 to +61
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@AsakuraMizu AsakuraMizu Nov 10, 2025

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Same here.

info!("Secondary CPU {:x} init OK.", cpu_id);
super::INITED_CPUS.fetch_add(1, Ordering::Release);

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