est: create via resistors in series between tree and pin nodes

src/cts/test/array.ok

@@ -136,8 +136,8 @@ legalized HPWL         193564.6 u
 delta HPWL                    0 %
 
 Clock clk
-   1.06 source latency inst_5_7/clk ^
-  -1.20 target latency inst_6_7/clk ^
+   1.07 source latency inst_5_7/clk ^
+  -1.21 target latency inst_6_7/clk ^
    0.00 CRPR
 --------------
   -0.14 setup skew
@@ -180,9 +180,9 @@ Path Type: max
    0.04    1.10 ^ wire9/Z (BUF_X8)
    0.05    1.15 ^ clkbuf_leaf_0_clk/Z (BUF_X4)
    0.00    1.15 ^ inst_1_1/clk (array_tile)
-   0.21    1.36 ^ inst_1_1/e_out (array_tile)
-   0.00    1.36 ^ inst_2_1/w_in (array_tile)
-           1.36   data arrival time
+   0.21    1.37 ^ inst_1_1/e_out (array_tile)
+   0.00    1.37 ^ inst_2_1/w_in (array_tile)
+           1.37   data arrival time
 
    5.00    5.00   clock clk (rise edge)
    0.00    5.00   clock source latency
@@ -219,7 +219,7 @@ Path Type: max
            6.05   data required time
 ---------------------------------------------------------
            6.05   data required time
-          -1.36   data arrival time
+          -1.37   data arrival time
 ---------------------------------------------------------
            4.69   slack (MET)
 

src/cts/test/array_ins_delay.ok

@@ -126,8 +126,8 @@ legalized HPWL         193564.6 u
 delta HPWL                    0 %
 
 Clock clk
-   1.06 source latency inst_5_7/clk ^
-  -1.20 target latency inst_6_7/clk ^
+   1.07 source latency inst_5_7/clk ^
+  -1.21 target latency inst_6_7/clk ^
    0.00 CRPR
 --------------
   -0.14 setup skew
@@ -170,9 +170,9 @@ Path Type: max
    0.04    1.10 ^ wire9/Z (BUF_X8)
    0.05    1.15 ^ clkbuf_leaf_0_clk/Z (BUF_X4)
    0.00    1.15 ^ inst_1_1/clk (array_tile)
-   0.21    1.36 ^ inst_1_1/e_out (array_tile)
-   0.00    1.36 ^ inst_2_1/w_in (array_tile)
-           1.36   data arrival time
+   0.21    1.37 ^ inst_1_1/e_out (array_tile)
+   0.00    1.37 ^ inst_2_1/w_in (array_tile)
+           1.37   data arrival time
 
    5.00    5.00   clock clk (rise edge)
    0.00    5.00   clock source latency
@@ -209,7 +209,7 @@ Path Type: max
            6.05   data required time
 ---------------------------------------------------------
            6.05   data required time
-          -1.36   data arrival time
+          -1.37   data arrival time
 ---------------------------------------------------------
            4.69   slack (MET)
 

src/cts/test/array_no_blockages.ok

@@ -126,7 +126,7 @@ delta HPWL                    1 %
 
 Clock clk
    1.03 source latency inst_5_4/clk ^
-  -1.14 target latency inst_6_4/clk ^
+  -1.15 target latency inst_6_4/clk ^
    0.00 CRPR
 --------------
   -0.12 setup skew

src/cts/test/array_repair_clock_nets.ok

@@ -139,7 +139,7 @@ delta HPWL                    0 %
 
 Clock clk
    1.08 source latency inst_5_7/clk ^
-  -1.21 target latency inst_6_7/clk ^
+  -1.22 target latency inst_6_7/clk ^
    0.00 CRPR
 --------------
   -0.14 setup skew
@@ -181,7 +181,7 @@ Path Type: max
    0.04    1.07 ^ wire11/Z (BUF_X8)
    0.04    1.11 ^ wire10/Z (BUF_X8)
    0.05    1.16 ^ clkbuf_leaf_0_clk/Z (BUF_X4)
-   0.00    1.16 ^ inst_1_1/clk (array_tile)
+   0.00    1.17 ^ inst_1_1/clk (array_tile)
    0.21    1.38 ^ inst_1_1/e_out (array_tile)
    0.00    1.38 ^ inst_2_1/w_in (array_tile)
            1.38   data arrival time

src/cts/test/skip_nets.ok

@@ -153,11 +153,12 @@ CTS config:
 [DEBUG CTS-insertion delay] new delay buffer delaybuf_1_clk is inserted at (53513 162428)
 [DEBUG CTS-insertion delay] new delay buffer delaybuf_2_clk is inserted at (53472 160552)
 [DEBUG CTS-insertion delay] new delay buffer delaybuf_3_clk is inserted at (53431 158676)
-[DEBUG CTS-insertion delay] new delay buffer delaybuf_4_clk is inserted at (100434 178107)
-[DEBUG CTS-insertion delay] new delay buffer delaybuf_5_clk is inserted at (100868 156355)
-[DEBUG CTS-insertion delay] new delay buffer delaybuf_6_clk is inserted at (101302 134603)
-[DEBUG CTS-insertion delay] new delay buffer delaybuf_7_clk is inserted at (101737 112851)
-[DEBUG CTS-insertion delay] new delay buffer delaybuf_8_clk is inserted at (102171 91099)
-[DEBUG CTS-insertion delay] new delay buffer delaybuf_9_clk is inserted at (102605 69347)
-[INFO CTS-0036]  inserted 10 delay buffers
-[INFO CTS-0037] Total number of delay buffers: 10
+[DEBUG CTS-insertion delay] new delay buffer delaybuf_4_clk is inserted at (100380 180826)
+[DEBUG CTS-insertion delay] new delay buffer delaybuf_5_clk is inserted at (100760 161793)
+[DEBUG CTS-insertion delay] new delay buffer delaybuf_6_clk is inserted at (101140 142760)
+[DEBUG CTS-insertion delay] new delay buffer delaybuf_7_clk is inserted at (101520 123727)
+[DEBUG CTS-insertion delay] new delay buffer delaybuf_8_clk is inserted at (101900 104694)
+[DEBUG CTS-insertion delay] new delay buffer delaybuf_9_clk is inserted at (102280 85661)
+[DEBUG CTS-insertion delay] new delay buffer delaybuf_10_clk is inserted at (102660 66628)
+[INFO CTS-0036]  inserted 11 delay buffers
+[INFO CTS-0037] Total number of delay buffers: 11

src/dbSta/src/SpefWriter.cc

@@ -208,6 +208,10 @@ void SpefWriter::writeNet(Corner* corner, const Net* net, Parasitic* parasitic)
   bool label = false;
   for (auto node : parasitics_->nodes(parasitic)) {
     if (parasitics_->pin(node) == nullptr) {
+      if (parasitics_->nodeGndCap(node) == 0) {
+        continue;
+      }
+
       if (!label) {
         label = true;
         stream << "*CAP" << '\n';
@@ -220,6 +224,9 @@ void SpefWriter::writeNet(Corner* corner, const Net* net, Parasitic* parasitic)
     }
   }
   for (auto cap : parasitics_->capacitors(parasitic)) {
+    if (parasitics_->value(cap) == 0) {
+      continue;
+    }
     if (!label) {
       label = true;
       stream << "*CAP" << '\n';

src/est/include/est/EstimateParasitics.h

@@ -256,7 +256,18 @@ class EstimateParasitics : public dbStaState
                                 size_t& resistor_id,
                                 Corner* corner,
                                 std::set<const Pin*>& connected_pins,
+                                const Net* net,
+                                int& max_node_index,
                                 bool is_clk);
+  void insertViaResistances(odb::dbTechLayer* pin_layer,
+                            odb::dbTechLayer* tree_layer,
+                            Parasitic* parasitic,
+                            ParasiticNode* pin_node,
+                            ParasiticNode* node,
+                            size_t& resistor_id,
+                            Corner* corner,
+                            const Net* net,
+                            int& max_node_index);
   void net2Pins(const Net* net, const Pin*& pin1, const Pin*& pin2) const;
   double dbuToMeters(int dist) const;
 

src/est/include/est/SteinerTree.h

@@ -114,6 +114,7 @@ class SteinerTree
   stt::Tree& fluteTree() { return tree_; }
   void createSteinerPtToPinMap();
   void locAddPin(const odb::Point& loc, const Pin* pin);
+  int getMaxIndex() const;
 
   static constexpr SteinerPt null_pt = -1;
 

src/est/src/EstimateParasitics.cpp

@@ -690,7 +690,8 @@ void EstimateParasitics::estimateWireParasiticSteiner(const Pin* drvr_pin,
       bool is_clk = global_router_->isNonLeafClock(db_network_->staToDb(net));
       double wire_cap = 0.0;
       double wire_res = 0.0;
-      int branch_count = tree->branchCount();
+      const int branch_count = tree->branchCount();
+      int max_node_index = tree->getMaxIndex();
       size_t resistor_id = 1;
       for (int i = 0; i < branch_count; i++) {
         odb::Point pt1, pt2;
@@ -766,6 +767,8 @@ void EstimateParasitics::estimateWireParasiticSteiner(const Pin* drvr_pin,
                                  resistor_id,
                                  corner,
                                  connected_pins,
+                                 net,
+                                 max_node_index,
                                  is_clk);
         parasiticNodeConnectPins(parasitic,
                                  n2,
@@ -774,6 +777,8 @@ void EstimateParasitics::estimateWireParasiticSteiner(const Pin* drvr_pin,
                                  resistor_id,
                                  corner,
                                  connected_pins,
+                                 net,
+                                 max_node_index,
                                  is_clk);
       }
       if (spef_writer) {
@@ -811,7 +816,8 @@ odb::dbTechLayer* EstimateParasitics::getPinLayer(const Pin* pin)
   if (iterm) {
     int min_layer_idx = std::numeric_limits<int>::max();
     for (const auto& [layer, rect] : iterm->getGeometries()) {
-      if (layer->getRoutingLevel() < min_layer_idx) {
+      if (layer->getType() == odb::dbTechLayerType::ROUTING
+          && layer->getRoutingLevel() < min_layer_idx) {
         min_layer_idx = layer->getRoutingLevel();
         pin_layer = layer;
       }
@@ -871,6 +877,8 @@ void EstimateParasitics::parasiticNodeConnectPins(
     size_t& resistor_id,
     Corner* corner,
     std::set<const Pin*>& connected_pins,
+    const Net* net,
+    int& max_node_index,
     const bool is_clk)
 {
   const PinSeq* pins = tree->pins(pt);
@@ -885,26 +893,19 @@ void EstimateParasitics::parasiticNodeConnectPins(
     for (const Pin* pin : *pins) {
       ParasiticNode* pin_node
           = parasitics_->ensureParasiticNode(parasitic, pin, network_);
-      if (connected_pins.find(pin) != connected_pins.end()) {
-        // If pin was already connected with via resistances, use a small
-        // resistor to keep connectivity intact.
-        parasitics_->makeResistor(
-            parasitic, resistor_id++, 1.0e-3, node, pin_node);
-      } else {
+      if (connected_pins.find(pin) == connected_pins.end()) {
         if (tree_layer != nullptr && !layer_res_.empty()) {
           odb::dbTechLayer* pin_layer = getPinLayer(pin);
-          for (int layer_number = pin_layer->getNumber();
-               layer_number < tree_layer->getNumber();
-               layer_number++) {
-            odb::dbTechLayer* cut_layer
-                = db_->getTech()->findLayer(layer_number);
-            if (cut_layer->getType() == odb::dbTechLayerType::CUT) {
-              double cut_res
-                  = std::max(layer_res_[layer_number][corner->index()], 1.0e-3);
-              parasitics_->makeResistor(
-                  parasitic, resistor_id++, cut_res, node, pin_node);
-            }
-          }
+
+          insertViaResistances(pin_layer,
+                               tree_layer,
+                               parasitic,
+                               pin_node,
+                               node,
+                               resistor_id,
+                               corner,
+                               net,
+                               max_node_index);
         } else {
           double cut_res
               = std::max(computeAverageCutResistance(corner), 1.0e-3);
@@ -917,6 +918,73 @@ void EstimateParasitics::parasiticNodeConnectPins(
   }
 }
 
+void EstimateParasitics::insertViaResistances(odb::dbTechLayer* pin_layer,
+                                              odb::dbTechLayer* tree_layer,
+                                              Parasitic* parasitic,
+                                              ParasiticNode* pin_node,
+                                              ParasiticNode* node,
+                                              size_t& resistor_id,
+                                              Corner* corner,
+                                              const Net* net,
+                                              int& max_node_index)
+{
+  ParasiticNode* prev_node = nullptr;
+
+  const int pin_layer_idx = pin_layer->getNumber();
+  const int tree_layer_idx = tree_layer->getNumber();
+  if (std::abs(pin_layer_idx - tree_layer->getNumber()) == 2) {
+    // Directly connect pin node and tree node if they are one cut layer apart
+    const int cut_layer_idx = pin_layer_idx < tree_layer_idx
+                                  ? pin_layer_idx + 1
+                                  : pin_layer_idx - 1;
+    const double cut_res
+        = std::max(layer_res_[cut_layer_idx][corner->index()], 1.0e-3);
+    parasitics_->makeResistor(
+        parasitic, resistor_id++, cut_res, pin_node, node);
+  } else if (pin_layer_idx == tree_layer_idx) {
+    // Add a small resistor between the pin node and tree node to keep
+    // connectivity
+    parasitics_->makeResistor(parasitic, resistor_id++, 1.0e-3, pin_node, node);
+  } else {
+    const auto [start_idx, end_idx]
+        = std::minmax(pin_layer_idx, tree_layer_idx);
+    const bool pin_is_below = (pin_layer_idx < tree_layer_idx);
+
+    for (int layer_idx = start_idx; layer_idx < end_idx; layer_idx++) {
+      odb::dbTechLayer* cut_layer = db_->getTech()->findLayer(layer_idx);
+      if (cut_layer->getType() != odb::dbTechLayerType::CUT) {
+        continue;
+      }
+      ParasiticNode* mid_node = parasitics_->ensureParasiticNode(
+          parasitic, net, ++max_node_index, network_);
+
+      const double cut_res
+          = std::max(layer_res_[layer_idx][corner->index()], 1.0e-3);
+
+      ParasiticNode* from_node = prev_node;
+      ParasiticNode* to_node = mid_node;
+      if (pin_is_below) {
+        if (layer_idx - 1 == pin_layer_idx) {
+          from_node = pin_node;
+        } else if (layer_idx + 1 == tree_layer_idx) {
+          to_node = node;
+        }
+      } else {
+        if (layer_idx - 1 == tree_layer_idx) {
+          from_node = node;
+        } else if (layer_idx + 1 == pin_layer_idx) {
+          to_node = pin_node;
+        }
+      }
+
+      parasitics_->makeResistor(
+          parasitic, resistor_id++, cut_res, from_node, to_node);
+
+      prev_node = mid_node;
+    }
+  }
+}
+
 void EstimateParasitics::net2Pins(const Net* net,
                                   const Pin*& pin1,
                                   const Pin*& pin2) const

src/est/src/SteinerTree.cpp

@@ -3,6 +3,7 @@
 
 #include "est/SteinerTree.h"
 
+#include <algorithm>
 #include <cmath>
 #include <cstddef>
 #include <string>
@@ -80,6 +81,18 @@ void SteinerTree::locAddPin(const odb::Point& loc, const Pin* pin)
   loc_pin_map_[loc].push_back(pin);
 }
 
+int SteinerTree::getMaxIndex() const
+{
+  int max_index = -1;
+  for (int i = 0; i < branchCount(); i++) {
+    const stt::Branch& branch_pt = tree_.branch[i];
+    max_index = std::max(max_index, i);
+    max_index = std::max({max_index, branch_pt.n});
+  }
+
+  return max_index;
+}
+
 void SteinerTree::branch(int index,
                          // Return values.
                          odb::Point& pt1,

src/est/test/make_parasitics4.ok

@@ -74,9 +74,9 @@ Path Type: max
    0.00    0.00 v in1 (in)
    0.02    0.02 v pad1/Y (PAD)
    0.34    0.37 v u1/Z (BUF_X1)
-   0.05    0.42 v pad2/PAD (PAD)
-   0.00    0.42 v out1 (out)
-           0.42   data arrival time
+   0.19    0.55 v pad2/PAD (PAD)
+   0.00    0.55 v out1 (out)
+           0.55   data arrival time
 ---------------------------------------------------------
 (Path is unconstrained)
 

src/est/test/make_parasitics6.ok

@@ -64,8 +64,8 @@ Corner: ss
 ----------------------------
 Net r1q
  Pin capacitance: 0.92-0.92
- Wire capacitance: 8.84-8.84
- Total capacitance: 9.76-9.76
+ Wire capacitance: 9.76-9.76
+ Total capacitance: 10.68-10.68
  Number of drivers: 1
  Number of loads: 1
  Number of pins: 2
@@ -78,8 +78,8 @@ Load pins
 
 Net r1q
  Pin capacitance: 0.83-0.89
- Wire capacitance: 13.75-13.81
- Total capacitance: 14.58-14.71
+ Wire capacitance: 14.64
+ Total capacitance: 15.47-15.54
  Number of drivers: 1
  Number of loads: 1
  Number of pins: 2