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Implement wrappers around the Architecture ID types #5431

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Implement wrappers around the Architecture ID types #5431

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c3d536e
Create types to represent Architecture ids, avoiding naked u32
rbran May 16, 2024
a0e715d
implement the field function for ArchitectureExt
rbran May 16, 2024
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109 changes: 48 additions & 61 deletions arch/riscv/src/lib.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -9,6 +9,7 @@ use std::fmt;
use std::hash::Hash;
use std::marker::PhantomData;

use binaryninja::architecture::{IntrinsicId, RegisterId};
use binaryninja::relocation::{Relocation, RelocationHandlerExt};
use binaryninja::{
add_optional_plugin_dependency, architecture,
Expand Down Expand Up @@ -81,7 +82,7 @@ enum Intrinsic {

#[derive(Copy, Clone)]
struct Register<D: 'static + RiscVDisassembler> {
id: u32,
id: RegisterId,
_dis: PhantomData<D>,
}

Expand All @@ -92,7 +93,7 @@ struct RiscVIntrinsic<D: 'static + RiscVDisassembler> {
}

impl<D: 'static + RiscVDisassembler> Register<D> {
fn new(id: u32) -> Self {
fn new(id: RegisterId) -> Self {
Self {
id,
_dis: PhantomData,
Expand All @@ -102,18 +103,18 @@ impl<D: 'static + RiscVDisassembler> Register<D> {
fn reg_type(&self) -> RegType {
let int_reg_count = <D::RegFile as RegFile>::int_reg_count();

if self.id < int_reg_count {
RegType::Integer(self.id)
if self.id.0 < int_reg_count {
RegType::Integer(self.id.0)
} else {
RegType::Float(self.id - int_reg_count)
RegType::Float(self.id.0 - int_reg_count)
}
}
}

impl<D: 'static + RiscVDisassembler> From<riscv_dis::IntReg<D>> for Register<D> {
fn from(reg: riscv_dis::IntReg<D>) -> Self {
Self {
id: reg.id(),
id: RegisterId(reg.id()),
_dis: PhantomData,
}
}
Expand All @@ -124,7 +125,7 @@ impl<D: 'static + RiscVDisassembler> From<FloatReg<D>> for Register<D> {
let int_reg_count = <D::RegFile as RegFile>::int_reg_count();

Self {
id: reg.id() + int_reg_count,
id: RegisterId(reg.id() + int_reg_count),
_dis: PhantomData,
}
}
Expand Down Expand Up @@ -191,7 +192,7 @@ impl<D: 'static + RiscVDisassembler> architecture::Register for Register<D> {
*self
}

fn id(&self) -> u32 {
fn id(&self) -> RegisterId {
self.id
}
}
Expand Down Expand Up @@ -268,7 +269,12 @@ impl<D: 'static + RiscVDisassembler + Send + Sync> fmt::Debug for Register<D> {
}

impl<D: RiscVDisassembler> RiscVIntrinsic<D> {
fn id_from_parts(id: u32, sz1: Option<u8>, sz2: Option<u8>, rm: Option<RoundMode>) -> u32 {
fn id_from_parts(
id: u32,
sz1: Option<u8>,
sz2: Option<u8>,
rm: Option<RoundMode>,
) -> IntrinsicId {
let sz1 = sz1.unwrap_or(0);
let sz2 = sz2.unwrap_or(0);
let rm = match rm {
Expand All @@ -284,13 +290,13 @@ impl<D: RiscVDisassembler> RiscVIntrinsic<D> {
id |= sz1 as u32;
id |= (sz2 as u32) << 8;
id |= (rm as u32) << 16;
id
IntrinsicId(id)
}

fn parts_from_id(id: u32) -> Option<(u32, u8, u8, RoundMode)> {
let sz1 = (id & 0xff) as u8;
let sz2 = ((id >> 8) & 0xff) as u8;
let rm = match (id >> 16) & 0xf {
fn parts_from_id(id: IntrinsicId) -> Option<(u32, u8, u8, RoundMode)> {
let sz1 = (id.0 & 0xff) as u8;
let sz2 = ((id.0 >> 8) & 0xff) as u8;
let rm = match (id.0 >> 16) & 0xf {
0 => RoundMode::Dynamic,
1 => RoundMode::RoundNearestEven,
2 => RoundMode::RoundTowardZero,
Expand All @@ -299,10 +305,10 @@ impl<D: RiscVDisassembler> RiscVIntrinsic<D> {
5 => RoundMode::RoundMaxMagnitude,
_ => return None,
};
Some(((id >> 20) & 0xfff, sz1, sz2, rm))
Some(((id.0 >> 20) & 0xfff, sz1, sz2, rm))
}

fn from_id(id: u32) -> Option<RiscVIntrinsic<D>> {
fn from_id(id: IntrinsicId) -> Option<RiscVIntrinsic<D>> {
match Self::parts_from_id(id) {
Some((0, _, _, _)) => Some(Intrinsic::Uret.into()),
Some((1, _, _, _)) => Some(Intrinsic::Sret.into()),
Expand Down Expand Up @@ -467,7 +473,7 @@ impl<D: RiscVDisassembler> architecture::Intrinsic for RiscVIntrinsic<D> {
}
}

fn id(&self) -> u32 {
fn id(&self) -> IntrinsicId {
match self.id {
Intrinsic::Uret => Self::id_from_parts(0, None, None, None),
Intrinsic::Sret => Self::id_from_parts(1, None, None, None),
Expand Down Expand Up @@ -1083,7 +1089,7 @@ impl<D: 'static + RiscVDisassembler + Send + Sync> architecture::Architecture fo
($op:ident, $t:expr, $f:expr) => {{
let rd = Register::from($op.rd());
match rd.id {
0 => $f.append(),
RegisterId(0) => $f.append(),
_ => il.set_reg(rd.size(), rd, $t).append(),
}
}};
Expand Down Expand Up @@ -1833,45 +1839,35 @@ impl<D: 'static + RiscVDisassembler + Send + Sync> architecture::Architecture fo
reg_count += 32;
}

let mut res = Vec::with_capacity(reg_count as usize);

for i in 0..reg_count {
res.push(Register::new(i));
}

res
(0..reg_count)
.map(|i| Register::new(RegisterId(i)))
.collect()
}

fn registers_full_width(&self) -> Vec<Self::Register> {
self.registers_all()
}

fn registers_global(&self) -> Vec<Self::Register> {
let mut regs = Vec::with_capacity(2);

for i in &[3, 4] {
regs.push(Register::new(*i));
}

regs
vec![Register::new(RegisterId(3)), Register::new(RegisterId(4))]
}

fn stack_pointer_reg(&self) -> Option<Self::Register> {
Some(Register::new(2))
Some(Register::new(RegisterId(2)))
}

fn link_reg(&self) -> Option<Self::Register> {
Some(Register::new(1))
Some(Register::new(RegisterId(1)))
}

fn register_from_id(&self, id: u32) -> Option<Self::Register> {
fn register_from_id(&self, id: RegisterId) -> Option<Self::Register> {
let mut reg_count = <D::RegFile as RegFile>::int_reg_count();

if <D::RegFile as RegFile>::Float::present() {
reg_count += 32;
}

if id > reg_count {
if id.0 > reg_count {
None
} else {
Some(Register::new(id))
Expand Down Expand Up @@ -1951,7 +1947,7 @@ impl<D: 'static + RiscVDisassembler + Send + Sync> architecture::Architecture fo
res.iter().map(|i| (*i).into()).collect()
}

fn intrinsic_from_id(&self, id: u32) -> Option<Self::Intrinsic> {
fn intrinsic_from_id(&self, id: IntrinsicId) -> Option<Self::Intrinsic> {
RiscVIntrinsic::from_id(id)
}

Expand Down Expand Up @@ -2632,15 +2628,15 @@ impl<D: 'static + RiscVDisassembler + Send + Sync> CallingConventionBase for Ris
1u32, 5, 6, 7, 10, 11, 12, 13, 14, 15, 16, 17, 28, 29, 30, 31,
] {
if i < &int_reg_count {
regs.push(Register::new(*i));
regs.push(Register::new(RegisterId(*i)));
}
}

if <D::RegFile as RegFile>::Float::present() {
for i in &[
0u32, 1, 2, 3, 4, 5, 6, 7, 10, 11, 12, 13, 14, 15, 16, 17, 28, 29, 30, 31,
] {
regs.push(Register::new(*i + int_reg_count));
regs.push(Register::new(RegisterId(*i + int_reg_count)));
}
}

Expand All @@ -2653,43 +2649,34 @@ impl<D: 'static + RiscVDisassembler + Send + Sync> CallingConventionBase for Ris

for i in &[8u32, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27] {
if i < &int_reg_count {
regs.push(Register::new(*i));
regs.push(Register::new(RegisterId(*i)));
}
}

if <D::RegFile as RegFile>::Float::present() {
for i in &[8u32, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27] {
regs.push(Register::new(*i + int_reg_count));
regs.push(Register::new(RegisterId(*i + int_reg_count)));
}
}

regs
}

fn int_arg_registers(&self) -> Vec<Register<D>> {
let mut regs = Vec::with_capacity(8);
let int_reg_count = <D::RegFile as RegFile>::int_reg_count();

for i in &[10, 11, 12, 13, 14, 15, 16, 17] {
if i < &int_reg_count {
regs.push(Register::new(*i));
}
}

regs
(10..=17)
.filter(|i| i < &int_reg_count)
.map(|i| Register::new(RegisterId(i)))
.collect()
}

fn float_arg_registers(&self) -> Vec<Register<D>> {
let mut regs = Vec::with_capacity(8);

if <D::RegFile as RegFile>::Float::present() {
let int_reg_count = <D::RegFile as RegFile>::int_reg_count();
for i in &[10, 11, 12, 13, 14, 15, 16, 17] {
regs.push(Register::new(*i + int_reg_count));
}
(10..=17).map(|i| Register::new(RegisterId(i + int_reg_count))).collect()
} else {
vec![]
}

regs
}

fn arg_registers_shared_index(&self) -> bool {
Expand All @@ -2709,25 +2696,25 @@ impl<D: 'static + RiscVDisassembler + Send + Sync> CallingConventionBase for Ris

// a0 == x10
fn return_int_reg(&self) -> Option<Register<D>> {
Some(Register::new(10))
Some(Register::new(RegisterId(10)))
}
// a1 == x11
fn return_hi_int_reg(&self) -> Option<Register<D>> {
Some(Register::new(11))
Some(Register::new(RegisterId(11)))
}

fn return_float_reg(&self) -> Option<Register<D>> {
if <D::RegFile as RegFile>::Float::present() {
let int_reg_count = <D::RegFile as RegFile>::int_reg_count();
Some(Register::new(10 + int_reg_count))
Some(Register::new(RegisterId(10 + int_reg_count)))
} else {
None
}
}

// gp == x3
fn global_pointer_reg(&self) -> Option<Register<D>> {
Some(Register::new(3))
Some(Register::new(RegisterId(3)))
}

fn implicitly_defined_registers(&self) -> Vec<Register<D>> {
Expand Down
4 changes: 2 additions & 2 deletions rust/examples/pdb-ng/src/symbol_parser.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -2010,13 +2010,13 @@ impl<'a, S: Source<'a> + 'a> PDBParserInstance<'a, S> {
self.log(|| format!("Register {:?} ==> {:?}", reg, xreg));
self.arch
.register_by_name(xreg.to_string().to_lowercase())
.map(|reg| reg.id() as i64)
.map(|reg| reg.id().0 as i64)
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id().into()?

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Maybe, but not using Into. Maybe something like reg.id().into_inner() or reg.raw_id().

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The as i64 can be replaced with .into(). But the .0 can only be replaced with a appropriated named function.

}
Some(AMD64(areg)) => {
self.log(|| format!("Register {:?} ==> {:?}", reg, areg));
self.arch
.register_by_name(areg.to_string().to_lowercase())
.map(|reg| reg.id() as i64)
.map(|reg| reg.id().0 as i64)
}
// TODO: Other arches
_ => None,
Expand Down
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