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When a 32-bit instruction is fetched over the course of two bus accesses, and the first half of the instruction is the halfword-of-interest, the check assumes the fetch of the first halfword doesn't fault. However it still permits faults on the second halfword. When this happens, the core takes a trap and clears the entire instruction reported on rvfi_insn. This does not match the expected halfword-of-interest so fails the check.

Fix by also preventing faults on imem_addr + 2 if imem_data is the first half of a 32-bit instruction. Note that imem_data can always be assumed to be the first half of an instruction as the assertions only fire when pc is equal to imem_addr.

The bus_imem check fails on Hazard3 without this change, and passes with it (depth=12). See discussion on #44

When a 32-bit instruction is fetched over the course of two
bus accesses, and the first half of the instruction is the
halfword-of-interest, the check assumes the fetch of the first halfword
doesn't fault. However it still permits faults on the second halfword.
When this happens, the core takes a trap and clears the entire
instruction reported on rvfi_insn. This does not match the expected
halfword-of-interest so fails the check.

Fix by also preventing faults on imem_addr + 2 if imem_data is the first
half of a 32-bit instruction. Note that imem_data can always be assumed
to be the first half of an instruction as the assertions only fire when
pc is equal to imem_addr.
@jix jix self-assigned this Sep 19, 2025
@jix jix merged commit 3a2512a into YosysHQ:main Oct 14, 2025
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2 participants