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Change generated kernel.xml axi manager port width to 512 (#1074)
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* Changed axi manager port width to 512

* Added comments regarding kernel width

Co-authored-by: Nathaniel Navarro <[email protected]>
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nathanielnrn and nathanielnrn authored Jul 7, 2022
1 parent ce7fce0 commit 585731f
Showing 1 changed file with 4 additions and 1 deletion.
5 changes: 4 additions & 1 deletion src/backend/xilinx/xml.rs
Original file line number Diff line number Diff line change
Expand Up @@ -150,7 +150,10 @@ impl Backend for XilinxXmlBackend {
name: axi_name,
mode: "master",
range: "0xFFFFFFFFFFFFFFFF",
data_width: 64,
// Width should match the bus data width of memory modules
// described in hardware, for example see
// https://github.com/cucapra/calyx/blob/c2b12a0fe6b1ee3aaaae0c66e7c4619ee6c82614/src/backend/xilinx/toplevel.rs#L58
data_width: 512,
port_type: "addressable",
base: "0x0",
});
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