Make inline prim input type explicit (#1970)

* make inline prim input type explicit * update tests --------- Co-authored-by: Rachit Nigam <[email protected]>
calyxir · Mar 14, 2024 · 67305da · 67305da
1 parent 23cd0a1
commit 67305da
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Showing 5 changed files with 22 additions and 24 deletions.
diff --git a/calyx-backend/src/verilog.rs b/calyx-backend/src/verilog.rs
@@ -179,7 +179,7 @@ fn emit_prim_inline<F: io::Write>(
         // NOTE: The signature port definitions are reversed inside the component.
         match port.direction {
             ir::Direction::Input => {
-                write!(f, "   input")?;
+                write!(f, "   input wire")?;
             }
             ir::Direction::Output => {
                 write!(f, "   output")?;

diff --git a/primitives/core.sv b/primitives/core.sv
@@ -6,7 +6,6 @@
  * - All parameter names must be SNAKE_CASE and all caps.
  * - Port names must be snake_case, no caps.
  */
-`default_nettype none
 
 module std_slice #(
     parameter IN_WIDTH  = 32,

diff --git a/tests/backend/verilog/big-const.expect b/tests/backend/verilog/big-const.expect
@@ -18,7 +18,7 @@ endmodule
 module std_wire #(
     parameter WIDTH = 32
 ) (
-   input logic [WIDTH-1:0] in,
+   input wire logic [WIDTH-1:0] in,
    output logic [WIDTH-1:0] out
 );
 assign out = in;
@@ -27,8 +27,8 @@ endmodule
 module std_add #(
     parameter WIDTH = 32
 ) (
-   input logic [WIDTH-1:0] left,
-   input logic [WIDTH-1:0] right,
+   input wire logic [WIDTH-1:0] left,
+   input wire logic [WIDTH-1:0] right,
    output logic [WIDTH-1:0] out
 );
 assign out = left + right;
@@ -37,10 +37,10 @@ endmodule
 module std_reg #(
     parameter WIDTH = 32
 ) (
-   input logic [WIDTH-1:0] in,
-   input logic write_en,
-   input logic clk,
-   input logic reset,
+   input wire logic [WIDTH-1:0] in,
+   input wire logic write_en,
+   input wire logic clk,
+   input wire logic reset,
    output logic [WIDTH-1:0] out,
    output logic done
 );

diff --git a/tests/backend/verilog/data-instance.expect b/tests/backend/verilog/data-instance.expect
@@ -18,7 +18,7 @@ endmodule
 module std_wire #(
     parameter WIDTH = 32
 ) (
-   input logic [WIDTH-1:0] in,
+   input wire logic [WIDTH-1:0] in,
    output logic [WIDTH-1:0] out
 );
 assign out = in;
@@ -27,8 +27,8 @@ endmodule
 module std_add #(
     parameter WIDTH = 32
 ) (
-   input logic [WIDTH-1:0] left,
-   input logic [WIDTH-1:0] right,
+   input wire logic [WIDTH-1:0] left,
+   input wire logic [WIDTH-1:0] right,
    output logic [WIDTH-1:0] out
 );
 assign out = left + right;
@@ -37,10 +37,10 @@ endmodule
 module std_reg #(
     parameter WIDTH = 32
 ) (
-   input logic [WIDTH-1:0] in,
-   input logic write_en,
-   input logic clk,
-   input logic reset,
+   input wire logic [WIDTH-1:0] in,
+   input wire logic write_en,
+   input wire logic clk,
+   input wire logic reset,
    output logic [WIDTH-1:0] out,
    output logic done
 );

diff --git a/tests/backend/verilog/memory-with-external-attribute.expect b/tests/backend/verilog/memory-with-external-attribute.expect
@@ -244,7 +244,6 @@ endmodule
  * - All parameter names must be SNAKE_CASE and all caps.
  * - Port names must be snake_case, no caps.
  */
-`default_nettype none
 
 module std_slice #(
     parameter IN_WIDTH  = 32,
@@ -500,7 +499,7 @@ endmodule
 module std_wire #(
     parameter WIDTH = 32
 ) (
-   input logic [WIDTH-1:0] in,
+   input wire logic [WIDTH-1:0] in,
    output logic [WIDTH-1:0] out
 );
 assign out = in;
@@ -509,8 +508,8 @@ endmodule
 module std_add #(
     parameter WIDTH = 32
 ) (
-   input logic [WIDTH-1:0] left,
-   input logic [WIDTH-1:0] right,
+   input wire logic [WIDTH-1:0] left,
+   input wire logic [WIDTH-1:0] right,
    output logic [WIDTH-1:0] out
 );
 assign out = left + right;
@@ -519,10 +518,10 @@ endmodule
 module std_reg #(
     parameter WIDTH = 32
 ) (
-   input logic [WIDTH-1:0] in,
-   input logic write_en,
-   input logic clk,
-   input logic reset,
+   input wire logic [WIDTH-1:0] in,
+   input wire logic write_en,
+   input wire logic clk,
+   input wire logic reset,
    output logic [WIDTH-1:0] out,
    output logic done
 );