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Add ap_idle generation #1101

Merged
merged 6 commits into from
Jul 15, 2022
Merged

Add ap_idle generation #1101

merged 6 commits into from
Jul 15, 2022

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nathanielnrn
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@nathanielnrn nathanielnrn commented Jul 14, 2022

Previously ap_idle signal was not generated, which led to some issues when running designs through PYNQ.
This adds generation and associated logic.

Fixes #1078 and is part of broader efforts of #1072

Previously ap_idle was not generated, which led to some issues running
designs through PYNQ.
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@sampsyo sampsyo left a comment

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Looks cool from here!!

Here's a meta-level idea: maybe we should have a simple Runt test or two for this AXI generation stuff. Then it would be possible, in a PR, to see the changes in the generated Verilog for a couple of examples.

@@ -294,8 +306,12 @@ impl AddressSpace {
}

// port writes to internal register logic
// reads only
// XXX(nathanielnrn) Why does this need to be seperate from the above write logic?
// Seems basically the same to me?
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Indeed; maybe this could be factored out into a function? Or maybe it would be too annoying because of the slight differences in flag values…

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Gave this a shot, indeed a bit annoying because of scope issues, the helper function has a bunch of arguments and imo is not much cleaner than how it is currently. I think refactoring this could be a small issue for later? Willing to work on this more though.

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Yeah, totally, makes sense to me! I can imagine how this would imply a broader refactoring that wouldn't be trivial.

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Just making sure, is this merge-ready in your opinion? @sampsyo or @rachitnigam

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sampsyo commented Jul 15, 2022

Yes, looks great to me!

@nathanielnrn nathanielnrn enabled auto-merge (squash) July 15, 2022 18:01
@nathanielnrn nathanielnrn merged commit 688be6a into master Jul 15, 2022
@nathanielnrn nathanielnrn deleted the ap-idle-fix branch July 15, 2022 18:10
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Add ap_idle signal
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