-
Notifications
You must be signed in to change notification settings - Fork 50
New issue
Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.
By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.
Already on GitHub? Sign in to your account
Add ap_idle generation #1101
Add ap_idle generation #1101
Conversation
Previously ap_idle was not generated, which led to some issues running designs through PYNQ.
There was a problem hiding this comment.
Choose a reason for hiding this comment
The reason will be displayed to describe this comment to others. Learn more.
Looks cool from here!!
Here's a meta-level idea: maybe we should have a simple Runt test or two for this AXI generation stuff. Then it would be possible, in a PR, to see the changes in the generated Verilog for a couple of examples.
@@ -294,8 +306,12 @@ impl AddressSpace { | |||
} | |||
|
|||
// port writes to internal register logic | |||
// reads only | |||
// XXX(nathanielnrn) Why does this need to be seperate from the above write logic? | |||
// Seems basically the same to me? |
There was a problem hiding this comment.
Choose a reason for hiding this comment
The reason will be displayed to describe this comment to others. Learn more.
Indeed; maybe this could be factored out into a function? Or maybe it would be too annoying because of the slight differences in flag values…
There was a problem hiding this comment.
Choose a reason for hiding this comment
The reason will be displayed to describe this comment to others. Learn more.
Gave this a shot, indeed a bit annoying because of scope issues, the helper function has a bunch of arguments and imo is not much cleaner than how it is currently. I think refactoring this could be a small issue for later? Willing to work on this more though.
There was a problem hiding this comment.
Choose a reason for hiding this comment
The reason will be displayed to describe this comment to others. Learn more.
Yeah, totally, makes sense to me! I can imagine how this would imply a broader refactoring that wouldn't be trivial.
Just making sure, is this merge-ready in your opinion? @sampsyo or @rachitnigam |
Yes, looks great to me! |
Previously ap_idle signal was not generated, which led to some issues when running designs through PYNQ.
This adds generation and associated logic.
Fixes #1078 and is part of broader efforts of #1072