Renaming script to allow multiple VeeR cores to coexist #230

koblonczek · 2024-08-20T14:28:20Z

This PR adds a script that seds relevant files and prefixes names of relevant entities so that multiple VeeR cores do not clash with each other during elaboration.

Usage instructions:

Generate VeeR configuration - these files should get generated: common_defines.vh, el2_param.vh, el2_pdef.vh and pd_defines.vh
At the top of the script set configuration variables: PREFIX to configure the prefix string, DEFINES_PATH to configure where files from step 1. reside and DESIGN_DIR to configure where the design directory with RTL sources resides
Run the script. RTL sources in DESIGN_DIR will be modified, new headers (as those in step 1.) with prefixed name will be generated in DEFINES_PATH and old ones removed to prevent them from redefining their contents if used with another VeeR instance

github-actions · 2024-08-20T16:49:42Z

Links to coverage and verification reports for this PR (#230) are available at https://chipsalliance.github.io/Cores-VeeR-EL2/

github-actions · 2024-08-20T18:32:49Z

Links to coverage and verification reports for this PR (#230) are available at https://chipsalliance.github.io/Cores-VeeR-EL2/

… module names Internal-tag: [#43412] Signed-off-by: Krzysztof Obłonczek <[email protected]>

…t directory, remove old header files Internal-tag: [#43412] Signed-off-by: Krzysztof Obłonczek <[email protected]>

Internal-tag: [#43412] Signed-off-by: Krzysztof Obłonczek <[email protected]>

Internal-tag: [#43412] Signed-off-by: Tomasz Michalak <[email protected]>

github-actions · 2024-10-24T21:17:51Z

Links to coverage and verification reports for this PR (#230) are available at https://chipsalliance.github.io/Cores-VeeR-EL2/

github-actions

Remaining comments which cannot be posted as a review comment to avoid GitHub Rate Limit

verible-verilog-lint

design/lib/axi4_to_ahb.sv|463 col 101| Line length exceeds max: 100; is: 160 [Style: line-length] [line-length]
design/lib/axi4_to_ahb.sv|464 col 101| Line length exceeds max: 100; is: 160 [Style: line-length] [line-length]
design/lib/axi4_to_ahb.sv|465 col 101| Line length exceeds max: 100; is: 160 [Style: line-length] [line-length]
design/ifu/el2_ifu.sv|22 col 8| Declared module does not match the first dot-delimited component of file name: "el2_ifu" [Style: file-names] [module-filename]
design/lsu/el2_lsu.sv|28 col 8| Declared module does not match the first dot-delimited component of file name: "el2_lsu" [Style: file-names] [module-filename]
design/el2_veer.sv|23 col 8| Declared module does not match the first dot-delimited component of file name: "el2_veer" [Style: file-names] [module-filename]
design/el2_veer.sv|850 col 101| Line length exceeds max: 100; is: 182 [Style: line-length] [line-length]
design/el2_veer.sv|851 col 101| Line length exceeds max: 100; is: 141 [Style: line-length] [line-length]
design/lsu/el2_lsu_lsc_ctl.sv|28 col 8| Declared module does not match the first dot-delimited component of file name: "el2_lsu_lsc_ctl" [Style: file-names] [module-filename]
design/el2_dma_ctrl.sv|24 col 8| Declared module does not match the first dot-delimited component of file name: "el2_dma_ctrl" [Style: file-names] [module-filename]
design/dmi/dmi_wrapper.v|24 col 8| Declared module does not match the first dot-delimited component of file name: "dmi_wrapper" [Style: file-names] [module-filename]
design/lsu/el2_lsu_trigger.sv|25 col 8| Declared module does not match the first dot-delimited component of file name: "el2_lsu_trigger" [Style: file-names] [module-filename]
design/exu/el2_exu.sv|17 col 8| Declared module does not match the first dot-delimited component of file name: "el2_exu" [Style: file-names] [module-filename]
design/exu/el2_exu.sv|160 col 101| Line length exceeds max: 100; is: 194 [Style: line-length] [line-length]
design/exu/el2_exu.sv|161 col 101| Line length exceeds max: 100; is: 194 [Style: line-length] [line-length]
design/exu/el2_exu.sv|162 col 101| Line length exceeds max: 100; is: 193 [Style: line-length] [line-length]
design/exu/el2_exu.sv|163 col 101| Line length exceeds max: 100; is: 194 [Style: line-length] [line-length]
design/exu/el2_exu.sv|164 col 101| Line length exceeds max: 100; is: 194 [Style: line-length] [line-length]
design/exu/el2_exu.sv|166 col 101| Line length exceeds max: 100; is: 217 [Style: line-length] [line-length]
design/exu/el2_exu.sv|169 col 101| Line length exceeds max: 100; is: 160 [Style: line-length] [line-length]
design/exu/el2_exu.sv|172 col 101| Line length exceeds max: 100; is: 193 [Style: line-length] [line-length]
design/exu/el2_exu.sv|173 col 101| Line length exceeds max: 100; is: 193 [Style: line-length] [line-length]
design/exu/el2_exu.sv|175 col 20| Pass named parameters for parameterized module instantiations with more than one parameter [Style: module-instantiation] [module-parameter]
design/exu/el2_exu.sv|175 col 101| Line length exceeds max: 100; is: 183 [Style: line-length] [line-length]
design/ifu/el2_ifu_ifc_ctl.sv|23 col 8| Declared module does not match the first dot-delimited component of file name: "el2_ifu_ifc_ctl" [Style: file-names] [module-filename]
design/ifu/el2_ifu_compress_ctl.sv|20 col 8| Declared module does not match the first dot-delimited component of file name: "el2_ifu_compress_ctl" [Style: file-names] [module-filename]
design/dmi/dmi_jtag_to_core_sync.v|25 col 8| Declared module does not match the first dot-delimited component of file name: "dmi_jtag_to_core_sync" [Style: file-names] [module-filename]
design/ifu/el2_ifu_mem_ctl.sv|24 col 8| Declared module does not match the first dot-delimited component of file name: "el2_ifu_mem_ctl" [Style: file-names] [module-filename]
design/el2_pic_ctrl.sv|535 col 42| Explicitly define a storage type for every parameter and localparam, (ID_BITS). [Style: constants] [explicit-parameter-storage-type]
design/el2_pic_ctrl.sv|560 col 8| Declared module does not match the first dot-delimited component of file name: "el2_pic_ctrl" [Style: file-names] [module-filename]
design/dbg/el2_dbg.sv|24 col 8| Declared module does not match the first dot-delimited component of file name: "el2_dbg" [Style: file-names] [module-filename]
design/dbg/el2_dbg.sv|298 col 101| Line length exceeds max: 100; is: 103 [Style: line-length] [line-length]
design/dbg/el2_dbg.sv|312 col 101| Line length exceeds max: 100; is: 166 [Style: line-length] [line-length]
design/dbg/el2_dbg.sv|313 col 101| Line length exceeds max: 100; is: 166 [Style: line-length] [line-length]
design/dbg/el2_dbg.sv|314 col 101| Line length exceeds max: 100; is: 166 [Style: line-length] [line-length]
design/dbg/el2_dbg.sv|315 col 101| Line length exceeds max: 100; is: 110 [Style: line-length] [line-length]
design/dbg/el2_dbg.sv|317 col 101| Line length exceeds max: 100; is: 166 [Style: line-length] [line-length]
design/dbg/el2_dbg.sv|344 col 101| Line length exceeds max: 100; is: 145 [Style: line-length] [line-length]
design/dbg/el2_dbg.sv|345 col 101| Line length exceeds max: 100; is: 145 [Style: line-length] [line-length]
design/dbg/el2_dbg.sv|352 col 101| Line length exceeds max: 100; is: 161 [Style: line-length] [line-length]
design/dbg/el2_dbg.sv|366 col 101| Line length exceeds max: 100; is: 230 [Style: line-length] [line-length]
design/dbg/el2_dbg.sv|367 col 101| Line length exceeds max: 100; is: 153 [Style: line-length] [line-length]
design/dbg/el2_dbg.sv|368 col 101| Line length exceeds max: 100; is: 127 [Style: line-length] [line-length]
design/dbg/el2_dbg.sv|394 col 101| Line length exceeds max: 100; is: 176 [Style: line-length] [line-length]
design/dbg/el2_dbg.sv|395 col 101| Line length exceeds max: 100; is: 170 [Style: line-length] [line-length]
design/dbg/el2_dbg.sv|396 col 101| Line length exceeds max: 100; is: 153 [Style: line-length] [line-length]
design/dbg/el2_dbg.sv|434 col 101| Line length exceeds max: 100; is: 168 [Style: line-length] [line-length]
design/dbg/el2_dbg.sv|435 col 101| Line length exceeds max: 100; is: 149 [Style: line-length] [line-length]
design/dbg/el2_dbg.sv|439 col 101| Line length exceeds max: 100; is: 173 [Style: line-length] [line-length]
design/dbg/el2_dbg.sv|451 col 101| Line length exceeds max: 100; is: 139 [Style: line-length] [line-length]
design/dbg/el2_dbg.sv|452 col 101| Line length exceeds max: 100; is: 141 [Style: line-length] [line-length]
design/dbg/el2_dbg.sv|453 col 101| Line length exceeds max: 100; is: 147 [Style: line-length] [line-length]
design/dbg/el2_dbg.sv|464 col 101| Line length exceeds max: 100; is: 131 [Style: line-length] [line-length]
design/dbg/el2_dbg.sv|474 col 101| Line length exceeds max: 100; is: 137 [Style: line-length] [line-length]
design/dbg/el2_dbg.sv|476 col 101| Line length exceeds max: 100; is: 173 [Style: line-length] [line-length]
design/dbg/el2_dbg.sv|477 col 101| Line length exceeds max: 100; is: 173 [Style: line-length] [line-length]
design/dbg/el2_dbg.sv|588 col 101| Line length exceeds max: 100; is: 161 [Style: line-length] [line-length]
design/dbg/el2_dbg.sv|589 col 101| Line length exceeds max: 100; is: 165 [Style: line-length] [line-length]
design/dbg/el2_dbg.sv|698 col 101| Line length exceeds max: 100; is: 148 [Style: line-length] [line-length]
design/dec/el2_dec_trigger.sv|25 col 8| Declared module does not match the first dot-delimited component of file name: "el2_dec_trigger" [Style: file-names] [module-filename]
design/lib/ahb_to_axi4.sv|23 col 8| Declared module does not match the first dot-delimited component of file name: "ahb_to_axi4" [Style: file-names] [module-filename]
design/lib/ahb_to_axi4.sv|196 col 101| Line length exceeds max: 100; is: 163 [Style: line-length] [line-length]
design/lib/ahb_to_axi4.sv|221 col 101| Line length exceeds max: 100; is: 167 [Style: line-length] [line-length]
design/lib/ahb_to_axi4.sv|222 col 101| Line length exceeds max: 100; is: 222 [Style: line-length] [line-length]
design/lib/ahb_to_axi4.sv|225 col 101| Line length exceeds max: 100; is: 160 [Style: line-length] [line-length]
design/lib/ahb_to_axi4.sv|226 col 101| Line length exceeds max: 100; is: 160 [Style: line-length] [line-length]
design/lib/ahb_to_axi4.sv|227 col 101| Line length exceeds max: 100; is: 160 [Style: line-length] [line-length]
design/lib/ahb_to_axi4.sv|228 col 101| Line length exceeds max: 100; is: 160 [Style: line-length] [line-length]
design/lib/ahb_to_axi4.sv|229 col 101| Line length exceeds max: 100; is: 160 [Style: line-length] [line-length]
design/lib/ahb_to_axi4.sv|230 col 101| Line length exceeds max: 100; is: 160 [Style: line-length] [line-length]
design/lib/ahb_to_axi4.sv|265 col 101| Line length exceeds max: 100; is: 199 [Style: line-length] [line-length]
design/lib/ahb_to_axi4.sv|266 col 101| Line length exceeds max: 100; is: 199 [Style: line-length] [line-length]
design/lib/ahb_to_axi4.sv|267 col 101| Line length exceeds max: 100; is: 199 [Style: line-length] [line-length]
design/lib/ahb_to_axi4.sv|268 col 101| Line length exceeds max: 100; is: 199 [Style: line-length] [line-length]
design/lib/ahb_to_axi4.sv|269 col 101| Line length exceeds max: 100; is: 161 [Style: line-length] [line-length]
design/lib/ahb_to_axi4.sv|270 col 101| Line length exceeds max: 100; is: 161 [Style: line-length] [line-length]
design/dec/el2_dec.sv|30 col 8| Declared module does not match the first dot-delimited component of file name: "el2_dec" [Style: file-names] [module-filename]
design/ifu/el2_ifu_ic_mem.sv|252 col 9| Macro name does not match the naming convention defined by regex pattern: [A-Z_0-9]+ [Style: defines] [macro-name-style]
design/ifu/el2_ifu_ic_mem.sv|403 col 9| Macro name does not match the naming convention defined by regex pattern: [A-Z_0-9]+ [Style: defines] [macro-name-style]
design/ifu/el2_ifu_ic_mem.sv|797 col 8| Declared module does not match the first dot-delimited component of file name: "el2_ifu_ic_mem" [Style: file-names] [module-filename]
design/ifu/el2_ifu_ic_mem.sv|961 col 15| Macro name does not match the naming convention defined by regex pattern: [A-Z_0-9]+ [Style: defines] [macro-name-style]
design/ifu/el2_ifu_ic_mem.sv|1163 col 9| Macro name does not match the naming convention defined by regex pattern: [A-Z_0-9]+ [Style: defines] [macro-name-style]
design/ifu/el2_ifu_bp_ctl.sv|27 col 8| Declared module does not match the first dot-delimited component of file name: "el2_ifu_bp_ctl" [Style: file-names] [module-filename]
design/dec/el2_dec_ib_ctl.sv|16 col 8| Declared module does not match the first dot-delimited component of file name: "el2_dec_ib_ctl" [Style: file-names] [module-filename]
design/ifu/el2_ifu_iccm_mem.sv|23 col 8| Declared module does not match the first dot-delimited component of file name: "el2_ifu_iccm_mem" [Style: file-names] [module-filename]
design/dec/el2_dec_gpr_ctl.sv|16 col 8| Declared module does not match the first dot-delimited component of file name: "el2_dec_gpr_ctl" [Style: file-names] [module-filename]
design/lsu/el2_lsu_addrcheck.sv|25 col 8| Declared module does not match the first dot-delimited component of file name: "el2_lsu_addrcheck" [Style: file-names] [module-filename]
design/el2_veer_wrapper.sv|24 col 8| Declared module does not match the first dot-delimited component of file name: "el2_veer_wrapper" [Style: file-names] [module-filename]
design/ifu/el2_ifu_aln_ctl.sv|21 col 8| Declared module does not match the first dot-delimited component of file name: "el2_ifu_aln_ctl" [Style: file-names] [module-filename]
design/dmi/dmi_mux.v|4 col 8| Declared module does not match the first dot-delimited component of file name: "dmi_mux" [Style: file-names] [module-filename]
design/dmi/rvjtag_tap.v|16 col 8| Declared module does not match the first dot-delimited component of file name: "rvjtag_tap" [Style: file-names] [module-filename]
design/dec/el2_dec_pmp_ctl.sv|26 col 8| Declared module does not match the first dot-delimited component of file name: "el2_dec_pmp_ctl" [Style: file-names] [module-filename]
design/lsu/el2_lsu_bus_intf.sv|25 col 8| Declared module does not match the first dot-delimited component of file name: "el2_lsu_bus_intf" [Style: file-names] [module-filename]
design/include/el2_def.sv|4 col 9| Package declaration name must match the file name (ignoring optional "_pkg" file name suffix). declaration: "veer0_el2_pkg" vs. basename(file): "el2_def" [Style: file-names] [package-filename]
design/lib/beh_lib.sv|19 col 33| Explicitly define a storage type for every parameter and localparam, (WIDTH). [Style: constants] [explicit-parameter-storage-type]
design/lib/beh_lib.sv|19 col 42| Explicitly define a storage type for every parameter and localparam, (SHORT). [Style: constants] [explicit-parameter-storage-type]
design/lib/beh_lib.sv|49 col 34| Explicitly define a storage type for every parameter and localparam, (WIDTH). [Style: constants] [explicit-parameter-storage-type]
design/lib/beh_lib.sv|49 col 43| Explicitly define a storage type for every parameter and localparam, (SHORT). [Style: constants] [explicit-parameter-storage-type]
design/lib/beh_lib.sv|68 col 35| Explicitly define a storage type for every parameter and localparam, (WIDTH). [Style: constants] [explicit-parameter-storage-type]
design/lib/beh_lib.sv|68 col 44| Explicitly define a storage type for every parameter and localparam, (SHORT). [Style: constants] [explicit-parameter-storage-type]
design/lib/beh_lib.sv|89 col 38| Explicitly define a storage type for every parameter and localparam, (WIDTH). [Style: constants] [explicit-parameter-storage-type]
design/lib/beh_lib.sv|89 col 47| Explicitly define a storage type for every parameter and localparam, (SHORT). [Style: constants] [explicit-parameter-storage-type]
design/lib/beh_lib.sv|113 col 39| Explicitly define a storage type for every parameter and localparam, (WIDTH). [Style: constants] [explicit-parameter-storage-type]
design/lib/beh_lib.sv|113 col 48| Explicitly define a storage type for every parameter and localparam, (SHORT). [Style: constants] [explicit-parameter-storage-type]
design/lib/beh_lib.sv|139 col 40| Explicitly define a storage type for every parameter and localparam, (WIDTH). [Style: constants] [explicit-parameter-storage-type]
design/lib/beh_lib.sv|139 col 49| Explicitly define a storage type for every parameter and localparam, (SHORT). [Style: constants] [explicit-parameter-storage-type]
design/lib/beh_lib.sv|158 col 101| Line length exceeds max: 100; is: 119 [Style: line-length] [line-length]
design/lib/beh_lib.sv|166 col 34| Explicitly define a storage type for every parameter and localparam, (WIDTH). [Style: constants] [explicit-parameter-storage-type]
design/lib/beh_lib.sv|166 col 43| Explicitly define a storage type for every parameter and localparam, (SHORT). [Style: constants] [explicit-parameter-storage-type]
design/lib/beh_lib.sv|166 col 52| Explicitly define a storage type for every parameter and localparam, (OVERRIDE). [Style: constants] [explicit-parameter-storage-type]
design/lib/beh_lib.sv|206 col 37| Explicitly define a storage type for every parameter and localparam, (WIDTH). [Style: constants] [explicit-parameter-storage-type]
design/lib/beh_lib.sv|239 col 36| Explicitly define a storage type for every parameter and localparam, (WIDTH). [Style: constants] [explicit-parameter-storage-type]
design/lib/beh_lib.sv|239 col 46| Explicitly define a storage type for every parameter and localparam, (LEFT). [Style: constants] [explicit-parameter-storage-type]
design/lib/beh_lib.sv|322 col 101| Line length exceeds max: 100; is: 134 [Style: line-length] [line-length]
design/lib/beh_lib.sv|337 col 35| Explicitly define a storage type for every parameter and localparam, (WIDTH). [Style: constants] [explicit-parameter-storage-type]
design/lib/beh_lib.sv|337 col 44| Explicitly define a storage type for every parameter and localparam, (OVERRIDE). [Style: constants] [explicit-parameter-storage-type]
design/lib/beh_lib.sv|380 col 36| Explicitly define a storage type for every parameter and localparam, (WIDTH). [Style: constants] [explicit-parameter-storage-type]
design/lib/beh_lib.sv|380 col 45| Explicitly define a storage type for every parameter and localparam, (OVERRIDE). [Style: constants] [explicit-parameter-storage-type]
design/lib/beh_lib.sv|416 col 35| Explicitly define a storage type for every parameter and localparam, (WIDTH). [Style: constants] [explicit-parameter-storage-type]
design/lib/beh_lib.sv|431 col 40| Explicitly define a storage type for every parameter and localparam, (WIDTH). [Style: constants] [explicit-parameter-storage-type]
design/lib/beh_lib.sv|443 col 101| Line length exceeds max: 100; is: 144 [Style: line-length] [line-length]
design/lib/beh_lib.sv|444 col 101| Line length exceeds max: 100; is: 141 [Style: line-length] [line-length]
design/lib/beh_lib.sv|510 col 38| Explicitly define a storage type for every parameter and localparam, (WIDTH). [Style: constants] [explicit-parameter-storage-type]
design/lib/beh_lib.sv|530 col 40| Explicitly define a storage type for every parameter and localparam, (WIDTH). [Style: constants] [explicit-parameter-storage-type]
design/lib/beh_lib.sv|530 col 50| Explicitly define a storage type for every parameter and localparam, (SHIFT). [Style: constants] [explicit-parameter-storage-type]
design/lib/beh_lib.sv|549 col 43| Explicitly define a storage type for every parameter and localparam, (WIDTH). [Style: constants] [explicit-parameter-storage-type]
design/lib/beh_lib.sv|569 col 42| Explicitly define a storage type for every parameter and localparam, (WIDTH). [Style: constants] [explicit-parameter-storage-type]
design/lib/beh_lib.sv|597 col 30| Explicitly define a storage type for every parameter and localparam, (CCM_SADR). [Style: constants] [explicit-parameter-storage-type]
design/lib/beh_lib.sv|622 col 33| Explicitly define a storage type for every parameter and localparam, (WIDTH). [Style: constants] [explicit-parameter-storage-type]
design/lib/beh_lib.sv|631 col 35| Explicitly define a storage type for every parameter and localparam, (WIDTH). [Style: constants] [explicit-parameter-storage-type]
design/lsu/el2_lsu_stbuf.sv|30 col 8| Declared module does not match the first dot-delimited component of file name: "el2_lsu_stbuf" [Style: file-names] [module-filename]
design/el2_mem.sv|19 col 8| Declared module does not match the first dot-delimited component of file name: "el2_mem" [Style: file-names] [module-filename]
design/lib/mem_lib.sv|86 col 24| Explicitly define a storage type for every parameter and localparam, (depth). [Style: constants] [explicit-parameter-storage-type]
design/lib/mem_lib.sv|86 col 36| Explicitly define a storage type for every parameter and localparam, (width). [Style: constants] [explicit-parameter-storage-type]
design/exu/el2_exu_mul_ctl.sv|17 col 8| Declared module does not match the first dot-delimited component of file name: "el2_exu_mul_ctl" [Style: file-names] [module-filename]
design/exu/el2_exu_mul_ctl.sv|180 col 101| Line length exceeds max: 100; is: 162 [Style: line-length] [line-length]
design/exu/el2_exu_mul_ctl.sv|181 col 101| Line length exceeds max: 100; is: 162 [Style: line-length] [line-length]
design/exu/el2_exu_mul_ctl.sv|726 col 101| Line length exceeds max: 100; is: 162 [Style: line-length] [line-length]
design/exu/el2_exu_div_ctl.sv|229 col 101| Line length exceeds max: 100; is: 148 [Style: line-length] [line-length]
design/exu/el2_exu_div_ctl.sv|230 col 101| Line length exceeds max: 100; is: 148 [Style: line-length] [line-length]
design/exu/el2_exu_div_ctl.sv|231 col 101| Line length exceeds max: 100; is: 148 [Style: line-length] [line-length]
design/exu/el2_exu_div_ctl.sv|507 col 101| Line length exceeds max: 100; is: 197 [Style: line-length] [line-length]
design/exu/el2_exu_div_ctl.sv|510 col 101| Line length exceeds max: 100; is: 123 [Style: line-length] [line-length]
design/exu/el2_exu_div_ctl.sv|511 col 101| Line length exceeds max: 100; is: 123 [Style: line-length] [line-length]
design/exu/el2_exu_div_ctl.sv|512 col 101| Line length exceeds max: 100; is: 123 [Style: line-length] [line-length]
design/exu/el2_exu_div_ctl.sv|513 col 101| Line length exceeds max: 100; is: 123 [Style: line-length] [line-length]
design/exu/el2_exu_div_ctl.sv|769 col 101| Line length exceeds max: 100; is: 197 [Style: line-length] [line-length]
design/exu/el2_exu_div_ctl.sv|772 col 101| Line length exceeds max: 100; is: 123 [Style: line-length] [line-length]
design/exu/el2_exu_div_ctl.sv|773 col 101| Line length exceeds max: 100; is: 123 [Style: line-length] [line-length]
design/exu/el2_exu_div_ctl.sv|774 col 101| Line length exceeds max: 100; is: 123 [Style: line-length] [line-length]
design/exu/el2_exu_div_ctl.sv|775 col 101| Line length exceeds max: 100; is: 123 [Style: line-length] [line-length]
design/exu/el2_exu_div_ctl.sv|1051 col 101| Line length exceeds max: 100; is: 197 [Style: line-length] [line-length]
design/exu/el2_exu_div_ctl.sv|1054 col 101| Line length exceeds max: 100; is: 123 [Style: line-length] [line-length]
design/exu/el2_exu_div_ctl.sv|1055 col 101| Line length exceeds max: 100; is: 123 [Style: line-length] [line-length]
design/exu/el2_exu_div_ctl.sv|1056 col 101| Line length exceeds max: 100; is: 123 [Style: line-length] [line-length]
design/exu/el2_exu_div_ctl.sv|1057 col 101| Line length exceeds max: 100; is: 123 [Style: line-length] [line-length]
design/exu/el2_exu_div_ctl.sv|1394 col 101| Line length exceeds max: 100; is: 198 [Style: line-length] [line-length]
design/exu/el2_exu_div_ctl.sv|1397 col 101| Line length exceeds max: 100; is: 124 [Style: line-length] [line-length]
design/exu/el2_exu_div_ctl.sv|1398 col 101| Line length exceeds max: 100; is: 124 [Style: line-length] [line-length]
design/exu/el2_exu_div_ctl.sv|1399 col 101| Line length exceeds max: 100; is: 124 [Style: line-length] [line-length]
design/exu/el2_exu_div_ctl.sv|1400 col 101| Line length exceeds max: 100; is: 124 [Style: line-length] [line-length]
design/exu/el2_exu_div_ctl.sv|1718 col 8| Declared module does not match the first dot-delimited component of file name: "el2_exu_div_ctl" [Style: file-names] [module-filename]
design/dec/el2_dec_tlu_ctl.sv|2721 col 8| Declared module does not match the first dot-delimited component of file name: "el2_dec_tlu_ctl" [Style: file-names] [module-filename]
design/el2_pmp.sv|17 col 8| Declared module does not match the first dot-delimited component of file name: "el2_pmp" [Style: file-names] [module-filename]
design/lsu/el2_lsu_ecc.sv|28 col 8| Declared module does not match the first dot-delimited component of file name: "el2_lsu_ecc" [Style: file-names] [module-filename]
design/lsu/el2_lsu_clkdomain.sv|26 col 8| Declared module does not match the first dot-delimited component of file name: "el2_lsu_clkdomain" [Style: file-names] [module-filename]
design/exu/el2_exu_alu_ctl.sv|17 col 8| Declared module does not match the first dot-delimited component of file name: "el2_exu_alu_ctl" [Style: file-names] [module-filename]
design/exu/el2_exu_alu_ctl.sv|209 col 101| Line length exceeds max: 100; is: 179 [Style: line-length] [line-length]
design/exu/el2_exu_alu_ctl.sv|210 col 101| Line length exceeds max: 100; is: 126 [Style: line-length] [line-length]

github-actions · 2024-10-25T19:13:40Z

design/ifu/el2_ifu_tb_memread.sv

+module veer0_el2_ifu_tb_memread;



⚠️ [verible-verilog-lint] _{reported by reviewdog 🐶}
Declared module does not match the first dot-delimited component of file name: "el2_ifu_tb_memread" [Style: file-names] [module-filename]

Suggested change

module veer0_el2_ifu_tb_memread;

module module el2_ifu_tb_memread;

github-actions · 2024-10-25T19:13:40Z

design/dec/el2_dec_decode_ctl.sv

+module veer0_el2_dec_dec_ctl
+  import veer0_el2_pkg::*;


⚠️ [verible-verilog-lint] _{reported by reviewdog 🐶}
Declared module does not match the first dot-delimited component of file name: "el2_dec_decode_ctl" [Style: file-names] [module-filename]

Suggested change

module veer0_el2_dec_dec_ctl

import veer0_el2_pkg::*;

module module el2_dec_decode_ctl

import veer0_el2_pkg::*;

github-actions · 2024-10-25T19:13:40Z

design/lsu/el2_lsu_dccm_ctl.sv

+module veer0_el2_lsu_dccm_ctl
+import veer0_el2_pkg::*;


⚠️ [verible-verilog-lint] _{reported by reviewdog 🐶}
Declared module does not match the first dot-delimited component of file name: "el2_lsu_dccm_ctl" [Style: file-names] [module-filename]

Suggested change

module veer0_el2_lsu_dccm_ctl

import veer0_el2_pkg::*;

module module el2_lsu_dccm_ctl

import veer0_el2_pkg::*;

github-actions · 2024-10-25T19:13:41Z

design/lsu/el2_lsu_dccm_mem.sv

+module veer0_el2_lsu_dccm_mem
+  import veer0_el2_pkg::*;


⚠️ [verible-verilog-lint] _{reported by reviewdog 🐶}
Declared module does not match the first dot-delimited component of file name: "el2_lsu_dccm_mem" [Style: file-names] [module-filename]

Suggested change

module veer0_el2_lsu_dccm_mem

import veer0_el2_pkg::*;

module module el2_lsu_dccm_mem

import veer0_el2_pkg::*;

github-actions · 2024-10-25T19:13:41Z

design/lsu/el2_lsu_bus_buffer.sv

+module veer0_el2_lsu_bus_buffer
+import veer0_el2_pkg::*;


⚠️ [verible-verilog-lint] _{reported by reviewdog 🐶}
Declared module does not match the first dot-delimited component of file name: "el2_lsu_bus_buffer" [Style: file-names] [module-filename]

Suggested change

module veer0_el2_lsu_bus_buffer

import veer0_el2_pkg::*;

module module el2_lsu_bus_buffer

import veer0_el2_pkg::*;

github-actions · 2024-10-25T19:13:43Z

design/lib/axi4_to_ahb.sv

-   rvdffs_fpga #(.WIDTH(1))   slvbuf_errorff  (.din(slvbuf_error_in),  .dout(slvbuf_error),        .en(slvbuf_error_en), .clk(bus_clk), .clken(bus_clk_en), .rawclk(clk), .*);
+   veer0_rvdffs_fpga #(.WIDTH(1))   slvbuf_writeff  (.din(buf_write),        .dout(slvbuf_write),        .en(slvbuf_wr_en),    .clk(buf_clk), .clken(buf_clken), .rawclk(clk), .*);
+   veer0_rvdffs_fpga #(.WIDTH(TAG)) slvbuf_tagff    (.din(buf_tag[TAG-1:0]), .dout(slvbuf_tag[TAG-1:0]), .en(slvbuf_wr_en),    .clk(buf_clk), .clken(buf_clken), .rawclk(clk), .*);
+   veer0_rvdffs_fpga #(.WIDTH(1))   slvbuf_errorff  (.din(slvbuf_error_in),  .dout(slvbuf_error),        .en(slvbuf_error_en), .clk(bus_clk), .clken(bus_clk_en), .rawclk(clk), .*);


⚠️ [verible-verilog-lint] _{reported by reviewdog 🐶}
Line length exceeds max: 100; is: 180 [Style: line-length] [line-length]

github-actions · 2024-10-25T19:13:43Z

design/lib/axi4_to_ahb.sv


-   rvdffsc_fpga #(.WIDTH(1)) buf_cmd_doneff     (.din(1'b1),                  .dout(cmd_doneQ),              .en(cmd_done),            .clear(cmd_done_rst), .clk(bus_clk), .clken(bus_clk_en), .rawclk(clk), .*);
-   rvdffs_fpga #(.WIDTH(3))  buf_cmd_byte_ptrff (.din(buf_cmd_byte_ptr[2:0]), .dout(buf_cmd_byte_ptrQ[2:0]), .en(buf_cmd_byte_ptr_en),                       .clk(bus_clk), .clken(bus_clk_en), .rawclk(clk), .*);
+   veer0_rvdffsc_fpga #(.WIDTH(1)) buf_cmd_doneff     (.din(1'b1),                  .dout(cmd_doneQ),              .en(cmd_done),            .clear(cmd_done_rst), .clk(bus_clk), .clken(bus_clk_en), .rawclk(clk), .*);


⚠️ [verible-verilog-lint] _{reported by reviewdog 🐶}
Line length exceeds max: 100; is: 216 [Style: line-length] [line-length]

github-actions · 2024-10-25T19:13:43Z

design/lib/axi4_to_ahb.sv

-   rvdffsc_fpga #(.WIDTH(1)) buf_cmd_doneff     (.din(1'b1),                  .dout(cmd_doneQ),              .en(cmd_done),            .clear(cmd_done_rst), .clk(bus_clk), .clken(bus_clk_en), .rawclk(clk), .*);
-   rvdffs_fpga #(.WIDTH(3))  buf_cmd_byte_ptrff (.din(buf_cmd_byte_ptr[2:0]), .dout(buf_cmd_byte_ptrQ[2:0]), .en(buf_cmd_byte_ptr_en),                       .clk(bus_clk), .clken(bus_clk_en), .rawclk(clk), .*);
+   veer0_rvdffsc_fpga #(.WIDTH(1)) buf_cmd_doneff     (.din(1'b1),                  .dout(cmd_doneQ),              .en(cmd_done),            .clear(cmd_done_rst), .clk(bus_clk), .clken(bus_clk_en), .rawclk(clk), .*);
+   veer0_rvdffs_fpga #(.WIDTH(3))  buf_cmd_byte_ptrff (.din(buf_cmd_byte_ptr[2:0]), .dout(buf_cmd_byte_ptrQ[2:0]), .en(buf_cmd_byte_ptr_en),                       .clk(bus_clk), .clken(bus_clk_en), .rawclk(clk), .*);


⚠️ [verible-verilog-lint] _{reported by reviewdog 🐶}
Line length exceeds max: 100; is: 216 [Style: line-length] [line-length]

github-actions · 2024-10-25T19:13:43Z

design/lib/axi4_to_ahb.sv

-   rvdff_fpga #(.WIDTH(1))  hwrite_ff (.din(ahb_hwrite),       .dout(ahb_hwrite_q),       .clk(bus_clk),       .clken(bus_clk_en),      .rawclk(clk), .*);
-   rvdff_fpga #(.WIDTH(1))  hresp_ff  (.din(ahb_hresp),        .dout(ahb_hresp_q),        .clk(bus_clk),       .clken(bus_clk_en),      .rawclk(clk), .*);
-   rvdff_fpga #(.WIDTH(64)) hrdata_ff (.din(ahb_hrdata[63:0]), .dout(ahb_hrdata_q[63:0]), .clk(ahbm_data_clk), .clken(ahbm_data_clken), .rawclk(clk), .*);
+   veer0_rvdff_fpga #(.WIDTH(1))  hready_ff (.din(ahb_hready),       .dout(ahb_hready_q),       .clk(bus_clk),       .clken(bus_clk_en),      .rawclk(clk), .*);


⚠️ [verible-verilog-lint] _{reported by reviewdog 🐶}
Line length exceeds max: 100; is: 160 [Style: line-length] [line-length]

github-actions · 2024-10-25T19:13:43Z

design/lib/axi4_to_ahb.sv

-   rvdff_fpga #(.WIDTH(1))  hresp_ff  (.din(ahb_hresp),        .dout(ahb_hresp_q),        .clk(bus_clk),       .clken(bus_clk_en),      .rawclk(clk), .*);
-   rvdff_fpga #(.WIDTH(64)) hrdata_ff (.din(ahb_hrdata[63:0]), .dout(ahb_hrdata_q[63:0]), .clk(ahbm_data_clk), .clken(ahbm_data_clken), .rawclk(clk), .*);
+   veer0_rvdff_fpga #(.WIDTH(1))  hready_ff (.din(ahb_hready),       .dout(ahb_hready_q),       .clk(bus_clk),       .clken(bus_clk_en),      .rawclk(clk), .*);
+   veer0_rvdff_fpga #(.WIDTH(2))  htrans_ff (.din(ahb_htrans[1:0]),  .dout(ahb_htrans_q[1:0]),  .clk(bus_clk),       .clken(bus_clk_en),      .rawclk(clk), .*);


⚠️ [verible-verilog-lint] _{reported by reviewdog 🐶}
Line length exceeds max: 100; is: 160 [Style: line-length] [line-length]

github-actions

Remaining comments which cannot be posted as a review comment to avoid GitHub Rate Limit

verible-verilog-format

github-actions · 2024-10-25T19:13:43Z

design/dbg/el2_dbg.sv

-module el2_dbg
-import el2_pkg::*;
+module veer0_el2_dbg
+import veer0_el2_pkg::*;


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

import veer0_el2_pkg::*;

import veer0_el2_pkg::*;

github-actions · 2024-10-25T19:13:43Z

design/dbg/el2_dbg.sv

   assign        sbcs_sbbusyerror_din = ~(sbcs_wren & dmi_reg_wdata[22]);   // Clear when writing one

-   rvdffs #(1) sbcs_sbbusyerror_reg  (.din(sbcs_sbbusyerror_din),  .dout(sbcs_reg[22]),    .en(sbcs_sbbusyerror_wren), .rst_l(dbg_dm_rst_l), .clk(sb_free_clk));
-   rvdffs #(1) sbcs_sbbusy_reg       (.din(sbcs_sbbusy_din),       .dout(sbcs_reg[21]),    .en(sbcs_sbbusy_wren),      .rst_l(dbg_dm_rst_l), .clk(sb_free_clk));
-   rvdffs #(1) sbcs_sbreadonaddr_reg (.din(dmi_reg_wdata[20]),     .dout(sbcs_reg[20]),    .en(sbcs_wren),             .rst_l(dbg_dm_rst_l), .clk(sb_free_clk));
-   rvdffs #(5) sbcs_misc_reg         (.din({dmi_reg_wdata[19],~dmi_reg_wdata[18],dmi_reg_wdata[17:15]}),
+   veer0_rvdffs #(1) sbcs_sbbusyerror_reg  (.din(sbcs_sbbusyerror_din),  .dout(sbcs_reg[22]),    .en(sbcs_sbbusyerror_wren), .rst_l(dbg_dm_rst_l), .clk(sb_free_clk));
+   veer0_rvdffs #(1) sbcs_sbbusy_reg       (.din(sbcs_sbbusy_din),       .dout(sbcs_reg[21]),    .en(sbcs_sbbusy_wren),      .rst_l(dbg_dm_rst_l), .clk(sb_free_clk));
+   veer0_rvdffs #(1) sbcs_sbreadonaddr_reg (.din(dmi_reg_wdata[20]),     .dout(sbcs_reg[20]),    .en(sbcs_wren),             .rst_l(dbg_dm_rst_l), .clk(sb_free_clk));
+   veer0_rvdffs #(5) sbcs_misc_reg         (.din({dmi_reg_wdata[19],~dmi_reg_wdata[18],dmi_reg_wdata[17:15]}),
                                      .dout(sbcs_reg_int[19:15]), .en(sbcs_wren),             .rst_l(dbg_dm_rst_l), .clk(sb_free_clk));
-   rvdffs #(3) sbcs_error_reg        (.din(sbcs_sberror_din[2:0]), .dout(sbcs_reg[14:12]), .en(sbcs_sberror_wren),     .rst_l(dbg_dm_rst_l), .clk(sb_free_clk));
+   veer0_rvdffs #(3) sbcs_error_reg        (.din(sbcs_sberror_din[2:0]), .dout(sbcs_reg[14:12]), .en(sbcs_sberror_wren),     .rst_l(dbg_dm_rst_l), .clk(sb_free_clk));

   assign sbcs_unaligned =    ((sbcs_reg[19:17] == 3'b001) &  sbaddress0_reg[0]) |


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

assign sbcs_sbbusyerror_din = ~(sbcs_wren & dmi_reg_wdata[22]); // Clear when writing one

rvdffs #(1) sbcs_sbbusyerror_reg (.din(sbcs_sbbusyerror_din), .dout(sbcs_reg[22]), .en(sbcs_sbbusyerror_wren), .rst_l(dbg_dm_rst_l), .clk(sb_free_clk));

rvdffs #(1) sbcs_sbbusy_reg (.din(sbcs_sbbusy_din), .dout(sbcs_reg[21]), .en(sbcs_sbbusy_wren), .rst_l(dbg_dm_rst_l), .clk(sb_free_clk));

rvdffs #(1) sbcs_sbreadonaddr_reg (.din(dmi_reg_wdata[20]), .dout(sbcs_reg[20]), .en(sbcs_wren), .rst_l(dbg_dm_rst_l), .clk(sb_free_clk));

rvdffs #(5) sbcs_misc_reg (.din({dmi_reg_wdata[19],~dmi_reg_wdata[18],dmi_reg_wdata[17:15]}),

veer0_rvdffs #(1) sbcs_sbbusyerror_reg (.din(sbcs_sbbusyerror_din), .dout(sbcs_reg[22]), .en(sbcs_sbbusyerror_wren), .rst_l(dbg_dm_rst_l), .clk(sb_free_clk));

veer0_rvdffs #(1) sbcs_sbbusy_reg (.din(sbcs_sbbusy_din), .dout(sbcs_reg[21]), .en(sbcs_sbbusy_wren), .rst_l(dbg_dm_rst_l), .clk(sb_free_clk));

veer0_rvdffs #(1) sbcs_sbreadonaddr_reg (.din(dmi_reg_wdata[20]), .dout(sbcs_reg[20]), .en(sbcs_wren), .rst_l(dbg_dm_rst_l), .clk(sb_free_clk));

veer0_rvdffs #(5) sbcs_misc_reg (.din({dmi_reg_wdata[19],~dmi_reg_wdata[18],dmi_reg_wdata[17:15]}),

.dout(sbcs_reg_int[19:15]), .en(sbcs_wren), .rst_l(dbg_dm_rst_l), .clk(sb_free_clk));

rvdffs #(3) sbcs_error_reg (.din(sbcs_sberror_din[2:0]), .dout(sbcs_reg[14:12]), .en(sbcs_sberror_wren), .rst_l(dbg_dm_rst_l), .clk(sb_free_clk));

veer0_rvdffs #(3) sbcs_error_reg (.din(sbcs_sberror_din[2:0]), .dout(sbcs_reg[14:12]), .en(sbcs_sberror_wren), .rst_l(dbg_dm_rst_l), .clk(sb_free_clk));

assign sbcs_unaligned = ((sbcs_reg[19:17] == 3'b001) & sbaddress0_reg[0]) |

assign sbcs_sbbusyerror_din = ~(sbcs_wren & dmi_reg_wdata[22]); // Clear when writing one

veer0_rvdffs #(1) sbcs_sbbusyerror_reg (

.din(sbcs_sbbusyerror_din),

.dout(sbcs_reg[22]),

.en(sbcs_sbbusyerror_wren),

.rst_l(dbg_dm_rst_l),

.clk(sb_free_clk)

);

veer0_rvdffs #(1) sbcs_sbbusy_reg (

.din(sbcs_sbbusy_din),

.dout(sbcs_reg[21]),

.en(sbcs_sbbusy_wren),

.rst_l(dbg_dm_rst_l),

.clk(sb_free_clk)

);

veer0_rvdffs #(1) sbcs_sbreadonaddr_reg (

.din(dmi_reg_wdata[20]),

.dout(sbcs_reg[20]),

.en(sbcs_wren),

.rst_l(dbg_dm_rst_l),

.clk(sb_free_clk)

);

veer0_rvdffs #(5) sbcs_misc_reg (

.din({dmi_reg_wdata[19], ~dmi_reg_wdata[18], dmi_reg_wdata[17:15]}),

.dout(sbcs_reg_int[19:15]),

.en(sbcs_wren),

.rst_l(dbg_dm_rst_l),

.clk(sb_free_clk)

);

veer0_rvdffs #(3) sbcs_error_reg (

.din(sbcs_sberror_din[2:0]),

.dout(sbcs_reg[14:12]),

.en(sbcs_sberror_wren),

.rst_l(dbg_dm_rst_l),

.clk(sb_free_clk)

);

assign sbcs_unaligned = ((sbcs_reg[19:17] == 3'b001) & sbaddress0_reg[0]) |

github-actions · 2024-10-25T19:13:43Z

design/dbg/el2_dbg.sv

@@ -341,15 +341,15 @@ import el2_pkg::*;
   assign        sbdata1_din[31:0]   = ({32{sbdata1_reg_wren0}} & dmi_reg_wdata[31:0]) |


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

assign sbdata1_din[31:0] = ({32{sbdata1_reg_wren0}} & dmi_reg_wdata[31:0]) |

assign sbdata1_din[31:0] = ({32{sbdata1_reg_wren0}} & dmi_reg_wdata[31:0]) |

github-actions · 2024-10-25T19:13:43Z

design/dbg/el2_dbg.sv

+   veer0_rvdffe #(32)    dbg_sbdata0_reg    (.*, .din(sbdata0_din[31:0]), .dout(sbdata0_reg[31:0]), .en(sbdata0_reg_wren), .rst_l(dbg_dm_rst_l));
+   veer0_rvdffe #(32)    dbg_sbdata1_reg    (.*, .din(sbdata1_din[31:0]), .dout(sbdata1_reg[31:0]), .en(sbdata1_reg_wren), .rst_l(dbg_dm_rst_l));

    // sbaddress
   assign        sbaddress0_reg_wren0   = dmi_reg_en & dmi_reg_wr_en & (dmi_reg_addr == 7'h39);
   assign        sbaddress0_reg_wren    = sbaddress0_reg_wren0 | sbaddress0_reg_wren1;
   assign        sbaddress0_reg_din[31:0]= ({32{sbaddress0_reg_wren0}} & dmi_reg_wdata[31:0]) |


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

veer0_rvdffe #(32) dbg_sbdata0_reg (.*, .din(sbdata0_din[31:0]), .dout(sbdata0_reg[31:0]), .en(sbdata0_reg_wren), .rst_l(dbg_dm_rst_l));

veer0_rvdffe #(32) dbg_sbdata1_reg (.*, .din(sbdata1_din[31:0]), .dout(sbdata1_reg[31:0]), .en(sbdata1_reg_wren), .rst_l(dbg_dm_rst_l));

// sbaddress

assign sbaddress0_reg_wren0 = dmi_reg_en & dmi_reg_wr_en & (dmi_reg_addr == 7'h39);

assign sbaddress0_reg_wren = sbaddress0_reg_wren0 | sbaddress0_reg_wren1;

assign sbaddress0_reg_din[31:0]= ({32{sbaddress0_reg_wren0}} & dmi_reg_wdata[31:0]) |

veer0_rvdffe #(32) dbg_sbdata0_reg (

.*,

.din(sbdata0_din[31:0]),

.dout(sbdata0_reg[31:0]),

.en(sbdata0_reg_wren),

.rst_l(dbg_dm_rst_l)

);

veer0_rvdffe #(32) dbg_sbdata1_reg (

.*,

.din(sbdata1_din[31:0]),

.dout(sbdata1_reg[31:0]),

.en(sbdata1_reg_wren),

.rst_l(dbg_dm_rst_l)

);

// sbaddress

assign sbaddress0_reg_wren0 = dmi_reg_en & dmi_reg_wr_en & (dmi_reg_addr == 7'h39);

assign sbaddress0_reg_wren = sbaddress0_reg_wren0 | sbaddress0_reg_wren1;

assign sbaddress0_reg_din[31:0]= ({32{sbaddress0_reg_wren0}} & dmi_reg_wdata[31:0]) |

github-actions · 2024-10-25T19:13:43Z

design/dbg/el2_dbg.sv

@@ -461,7 +461,7 @@ import el2_pkg::*;
                              ({32{data0_reg_wren1}} & core_dbg_rddata[31:0]) |
                              ({32{data0_reg_wren2}} & sb_bus_rdata[31:0]);

-   rvdffe #(32) dbg_data0_reg (.*, .din(data0_din[31:0]), .dout(data0_reg[31:0]), .en(data0_reg_wren), .rst_l(dbg_dm_rst_l));
+   veer0_rvdffe #(32) dbg_data0_reg (.*, .din(data0_din[31:0]), .dout(data0_reg[31:0]), .en(data0_reg_wren), .rst_l(dbg_dm_rst_l));


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

veer0_rvdffe #(32) dbg_data0_reg (.*, .din(data0_din[31:0]), .dout(data0_reg[31:0]), .en(data0_reg_wren), .rst_l(dbg_dm_rst_l));

veer0_rvdffe #(32) dbg_data0_reg (

.*,

.din(data0_din[31:0]),

.dout(data0_reg[31:0]),

.en(data0_reg_wren),

.rst_l(dbg_dm_rst_l)

);

github-actions · 2024-10-25T19:13:46Z

design/dec/el2_dec_decode_ctl.sv

@@ -1258,15 +1258,15 @@ end : cam_array



-   rvdfflie #( .WIDTH($bits(el2_trap_pkt_t)),.LEFT(9) ) trap_xff (.*, .en(i0_x_ctl_en), .din(d_t),  .dout(x_t));
+   veer0_rvdfflie #( .WIDTH($bits(el2_trap_pkt_t)),.LEFT(9) ) trap_xff (.*, .en(i0_x_ctl_en), .din(d_t),  .dout(x_t));


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

veer0_rvdfflie #( .WIDTH($bits(el2_trap_pkt_t)),.LEFT(9) ) trap_xff (.*, .en(i0_x_ctl_en), .din(d_t), .dout(x_t));

veer0_rvdfflie #(

.WIDTH($bits(el2_trap_pkt_t)),

.LEFT (9)

) trap_xff (

.*,

.en (i0_x_ctl_en),

.din (d_t),

.dout(x_t)

);

github-actions · 2024-10-25T19:13:46Z

design/dec/el2_dec_decode_ctl.sv


   always_comb begin
      x_t_in = x_t;
      x_t_in.i0trigger[3:0] = x_t.i0trigger & ~{4{dec_tlu_flush_lower_wb}};
   end


-   rvdfflie  #( .WIDTH($bits(el2_trap_pkt_t)),.LEFT(9) ) trap_r_ff (.*, .en(i0_x_ctl_en), .din(x_t_in),  .dout(r_t));
+   veer0_rvdfflie  #( .WIDTH($bits(el2_trap_pkt_t)),.LEFT(9) ) trap_r_ff (.*, .en(i0_x_ctl_en), .din(x_t_in),  .dout(r_t));


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

veer0_rvdfflie #( .WIDTH($bits(el2_trap_pkt_t)),.LEFT(9) ) trap_r_ff (.*, .en(i0_x_ctl_en), .din(x_t_in), .dout(r_t));

veer0_rvdfflie #(

.WIDTH($bits(el2_trap_pkt_t)),

.LEFT (9)

) trap_r_ff (

.*,

.en (i0_x_ctl_en),

.din (x_t_in),

.dout(r_t)

);

github-actions · 2024-10-25T19:13:46Z

design/dec/el2_dec_decode_ctl.sv


   always_comb begin
      x_t_in = x_t;
      x_t_in.i0trigger[3:0] = x_t.i0trigger & ~{4{dec_tlu_flush_lower_wb}};
   end


-   rvdfflie  #( .WIDTH($bits(el2_trap_pkt_t)),.LEFT(9) ) trap_r_ff (.*, .en(i0_x_ctl_en), .din(x_t_in),  .dout(r_t));
+   veer0_rvdfflie  #( .WIDTH($bits(el2_trap_pkt_t)),.LEFT(9) ) trap_r_ff (.*, .en(i0_x_ctl_en), .din(x_t_in),  .dout(r_t));


    always_comb begin


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

always_comb begin

always_comb begin

github-actions · 2024-10-25T19:13:46Z

design/dec/el2_dec_decode_ctl.sv

+   veer0_rvdffs #( $bits(el2_class_pkt_t) ) i0_x_c_ff   (.*, .en(i0_x_ctl_en),  .clk(active_clk), .din(i0_d_c),  .dout(i0_x_c));
+   veer0_rvdffs #( $bits(el2_class_pkt_t) ) i0_r_c_ff   (.*, .en(i0_r_ctl_en),  .clk(active_clk), .din(i0_x_c),  .dout(i0_r_c));


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

veer0_rvdffs #( $bits(el2_class_pkt_t) ) i0_x_c_ff (.*, .en(i0_x_ctl_en), .clk(active_clk), .din(i0_d_c), .dout(i0_x_c));

veer0_rvdffs #( $bits(el2_class_pkt_t) ) i0_r_c_ff (.*, .en(i0_r_ctl_en), .clk(active_clk), .din(i0_x_c), .dout(i0_r_c));

veer0_rvdffs #($bits(

el2_class_pkt_t

)) i0_x_c_ff (

.*,

.en (i0_x_ctl_en),

.clk (active_clk),

.din (i0_d_c),

.dout(i0_x_c)

);

veer0_rvdffs #($bits(

el2_class_pkt_t

)) i0_r_c_ff (

.*,

.en (i0_r_ctl_en),

.clk (active_clk),

.din (i0_x_c),

.dout(i0_r_c)

);

github-actions · 2024-10-25T19:13:46Z

design/dec/el2_dec_decode_ctl.sv

@@ -1314,7 +1314,7 @@ end : cam_array
   assign d_d.csraddr[11:0] =  i0[31:20]; // csr read/write address


-   rvdff  #(3) i0cgff               (.*, .clk(active_clk),            .din(i0_pipe_en[3:1]), .dout(i0_pipe_en[2:0]));
+   veer0_rvdff  #(3) i0cgff               (.*, .clk(active_clk),            .din(i0_pipe_en[3:1]), .dout(i0_pipe_en[2:0]));


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

veer0_rvdff #(3) i0cgff (.*, .clk(active_clk), .din(i0_pipe_en[3:1]), .dout(i0_pipe_en[2:0]));

veer0_rvdff #(3) i0cgff (

.*,

.clk (active_clk),

.din (i0_pipe_en[3:1]),

.dout(i0_pipe_en[2:0])

);

Internal-tag: [#43412] Signed-off-by: Tomasz Michalak <[email protected]>

tmichalak · 2024-10-25T19:28:42Z

@nileshbpat @calebofearth I updated the script to use regex with lookaheads and lookbehinds, preventing the prefix from being added if it already exists, enabling incremental updates. I added several log messages to the script as well.

github-actions · 2024-10-25T21:20:24Z

Links to coverage and verification reports for this PR (#230) are available at https://chipsalliance.github.io/Cores-VeeR-EL2/

Internal-tag: [#43412] Signed-off-by: Tomasz Michalak <[email protected]>

tmichalak marked this pull request as ready for review September 24, 2024 14:40

tmichalak force-pushed the 43412-unique-macro-names branch from 3835782 to 8383e68 Compare October 23, 2024 22:09

koblonczek and others added 10 commits October 24, 2024 13:18

Add script that adds custom prefixes to macros, main param struct and…

8f2d9c8

… module names Internal-tag: [#43412] Signed-off-by: Krzysztof Obłonczek <[email protected]>

Remove substituting names in makefiles, point default paths to curren…

0dcd4f9

…t directory, remove old header files Internal-tag: [#43412] Signed-off-by: Krzysztof Obłonczek <[email protected]>

Avoid processing some files twice

4c86ea4

Internal-tag: [#43412] Signed-off-by: Krzysztof Obłonczek <[email protected]>

Preserve prefix and suffix characters of a module name

38e6e40

Internal-tag: [#43412] Signed-off-by: Krzysztof Obłonczek <[email protected]>

Allow module name to start immediately following a newline

90dc196

Internal-tag: [#43412] Signed-off-by: Krzysztof Obłonczek <[email protected]>

Allow macros as module names, include verilog files in renaming

3c428c1

Internal-tag: [#43412] Signed-off-by: Krzysztof Obłonczek <[email protected]>

Prefix memory interface

bef3b85

Internal-tag: [#43412] Signed-off-by: Krzysztof Obłonczek <[email protected]>

Prefix memory macro names in el2_ifu_ic_mem.sv

b520d39

Internal-tag: [#43412] Signed-off-by: Krzysztof Obłonczek <[email protected]>

Fix prefixing define names in ifdefs and ifndefs

dd9ec18

Internal-tag: [#43412] Signed-off-by: Krzysztof Obłonczek <[email protected]>

tools: Allow to override default variables

82b6321

Internal-tag: [#43412] Signed-off-by: Tomasz Michalak <[email protected]>

tmichalak force-pushed the 43412-unique-macro-names branch from 8383e68 to 17924b3 Compare October 24, 2024 11:20

tools: Add logs and debug messages

d32bdfd

Internal-tag: [#43412] Signed-off-by: Tomasz Michalak <[email protected]>

tmichalak force-pushed the 43412-unique-macro-names branch from 17924b3 to d32bdfd Compare October 24, 2024 18:55

tmichalak force-pushed the 43412-unique-macro-names branch from 4e404b5 to ea81b13 Compare October 25, 2024 19:12

github-actions bot reviewed Oct 25, 2024

View reviewed changes

tmichalak added 2 commits October 25, 2024 21:26

tools: Don't process already processed instantiations

825afbe

Internal-tag: [#43412] Signed-off-by: Tomasz Michalak <[email protected]>

tools: Don't prefix already prefixed memory macro names

9603e83

Internal-tag: [#43412] Signed-off-by: Tomasz Michalak <[email protected]>

tmichalak force-pushed the 43412-unique-macro-names branch from ea81b13 to 9603e83 Compare October 25, 2024 19:27

tools: Add option to specify EXTRA_DESIGN_FILES

3475f1d

Internal-tag: [#43412] Signed-off-by: Tomasz Michalak <[email protected]>

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Renaming script to allow multiple VeeR cores to coexist #230

Renaming script to allow multiple VeeR cores to coexist #230

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tmichalak commented Oct 25, 2024

github-actions bot commented Oct 25, 2024

	module veer0_el2_ifu_tb_memread;
	module module el2_ifu_tb_memread;

		@@ -341,15 +341,15 @@ import el2_pkg::*;
		assign sbdata1_din[31:0] = ({32{sbdata1_reg_wren0}} & dmi_reg_wdata[31:0]) \|

		@@ -1258,15 +1258,15 @@ end : cam_array



		rvdfflie #( .WIDTH($bits(el2_trap_pkt_t)),.LEFT(9) ) trap_xff (.*, .en(i0_x_ctl_en), .din(d_t), .dout(x_t));
		veer0_rvdfflie #( .WIDTH($bits(el2_trap_pkt_t)),.LEFT(9) ) trap_xff (.*, .en(i0_x_ctl_en), .din(d_t), .dout(x_t));

		veer0_rvdffs #( $bits(el2_class_pkt_t) ) i0_x_c_ff (.*, .en(i0_x_ctl_en), .clk(active_clk), .din(i0_d_c), .dout(i0_x_c));
		veer0_rvdffs #( $bits(el2_class_pkt_t) ) i0_r_c_ff (.*, .en(i0_r_ctl_en), .clk(active_clk), .din(i0_x_c), .dout(i0_r_c));

-   veer0_rvdffs #( $bits(el2_class_pkt_t) ) i0_x_c_ff   (.*, .en(i0_x_ctl_en),  .clk(active_clk), .din(i0_d_c),  .dout(i0_x_c));
-   veer0_rvdffs #( $bits(el2_class_pkt_t) ) i0_r_c_ff   (.*, .en(i0_r_ctl_en),  .clk(active_clk), .din(i0_x_c),  .dout(i0_r_c));
+  veer0_rvdffs #($bits(
+      el2_class_pkt_t
+  )) i0_x_c_ff (
+      .*,
+      .en  (i0_x_ctl_en),
+      .clk (active_clk),
+      .din (i0_d_c),
+      .dout(i0_x_c)
+  );
+  veer0_rvdffs #($bits(
+      el2_class_pkt_t
+  )) i0_r_c_ff (
+      .*,
+      .en  (i0_r_ctl_en),
+      .clk (active_clk),
+      .din (i0_x_c),
+      .dout(i0_r_c)
+  );

Renaming script to allow multiple VeeR cores to coexist #230

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Renaming script to allow multiple VeeR cores to coexist #230

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tmichalak commented Oct 25, 2024

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