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Don't remove always blocks from uhdmtopModules #1880

Don't remove always blocks from uhdmtopModules

Don't remove always blocks from uhdmtopModules #1880

Workflow file for this run

name: 'yosys-systemverilog-plugin'
on:
push:
branches:
- master
pull_request:
jobs:
test-plugin:
runs-on: [self-hosted, Linux, X64, gcp-custom-runners]
container: ubuntu:jammy
defaults:
run:
shell: bash
strategy:
fail-fast: true
env:
CC: gcc-9
CXX: g++-9
CCACHE_DIR: "/root/Surelog/Surelog/.cache/"
DEBIAN_FRONTEND: noninteractive
steps:
- name: Install dependencies
run: |
apt-get update -qq
apt install -y software-properties-common
add-apt-repository ppa:ubuntu-toolchain-r/test
apt-get update -qq
apt install -y gcc-9 g++-9 build-essential cmake tclsh ant default-jre swig google-perftools libgoogle-perftools-dev python3 python3-dev python3-pip uuid uuid-dev tcl-dev flex libfl-dev git pkg-config libreadline-dev bison libffi-dev wget libtinfo5
update-alternatives --install /usr/bin/python python /usr/bin/python3 1
update-alternatives --install /usr/bin/pip pip /usr/bin/pip3 1
pip install orderedmultidict
- name: Setup plugin repository
run: |
# Github dropped support for unauthorized git: https://github.blog/2021-09-01-improving-git-protocol-security-github/
# Make sure we always use https:// instead of git://
#git config --global url.https://github.com/.insteadOf git://github.com/
# Use current main of the plugin repository...
git clone https://github.com/alaindargelas/synlig.git
cd synlig
git checkout stable_rs
git submodule sync
git submodule update --depth 3 --init --recursive --checkout \
./third_party/{surelog,yosys,make_env,yosys_f4pga_plugins,ibex} \
;
- name: Create Cache Timestamp
id: cache_timestamp
uses: nanzm/[email protected]
with:
format: 'YYYY-MM-DD-HH-mm-ss'
- name: Setup cache
uses: actions/cache@v2
with:
path: ${{ env.CCACHE_DIR }}
key: cache_${{ steps.cache_timestamp.outputs.time }}
restore-keys: cache_
- name: Build binaries
run: |
cd synlig
make -rR -j $(nproc) -Oline -f build_binaries.mk SYSTEMVERILOG_PLUGIN_ONLY:=0 \
install-surelog install-yosys install-plugins
- name: Setup build environment
run: |
# Environment creation has to be run with one job to avoid race conditions.
# See: https://github.com/SymbiFlow/make-env/pull/40
# Even with the fix more jobs doesn't help with anything.
pip install virtualenv
cd synlig
make -C ./tests env TEST=ibex -j1
- name: Build & Test
run: |
pip install virtualenv
cd synlig
make -C tests uhdm/yosys/synth-ibex-f4pga TEST=ibex \
ENABLE_READLINE=0 PRETTY=0 -j $(nproc)
- uses: actions/upload-artifact@v2
with:
name: top_artya7.bit
path: ./tests/build/lowrisc_ibex_top_artya7_surelog_0.1/synth-symbiflow/top_artya7.bit
- name: Upload load graphs
uses: actions/upload-artifact@v2
with:
name: plots
path: |
**/plot_*.svg