Merge pull request #3605 from alainmarcel/alainmarcel-patch-1

wip non-elab primitive instances
chipsalliance · Apr 19, 2023 · 5adf8a2 · 5adf8a2
2 parents 4e4e741 + bfddb1a
commit 5adf8a2
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Showing 157 changed files with 4,930 additions and 857 deletions.
diff --git a/include/Surelog/Design/ModuleDefinition.h b/include/Surelog/Design/ModuleDefinition.h
@@ -103,6 +103,14 @@ class ModuleDefinition : public DesignComponent, public ClockingBlockHolder {
   void setRefModules(std::vector<UHDM::ref_module*>* modules) {
     m_ref_modules = modules;
   }
+
+  UHDM::VectorOfprimitive* getPrimitives() { return m_subPrimitives; }
+  UHDM::VectorOfprimitive_array* getPrimitiveArrays() { return m_subPrimitiveArrays; }
+  UHDM::VectorOfgen_scope_array* getGenScopeArrays() { return m_subGenScopeArrays; }
+
+  void setPrimitives(UHDM::VectorOfprimitive* primitives) { m_subPrimitives = primitives; }
+  void setPrimitiveArrays(UHDM::VectorOfprimitive_array* primitives) { m_subPrimitiveArrays = primitives; }
+  void setGenScpeArrays(UHDM::VectorOfgen_scope_array* gen_arrays) { m_subGenScopeArrays = gen_arrays; }
 
  private:
   const std::string m_name;
@@ -115,6 +123,10 @@ class ModuleDefinition : public DesignComponent, public ClockingBlockHolder {
   UHDM::VectorOfattribute* attributes_ = nullptr;
   std::vector<UHDM::module_array*>* m_moduleArrays = nullptr;
   std::vector<UHDM::ref_module*>* m_ref_modules = nullptr;
+  UHDM::VectorOfprimitive* m_subPrimitives = nullptr;
+  UHDM::VectorOfprimitive_array* m_subPrimitiveArrays = nullptr;
+  UHDM::VectorOfgen_scope_array* m_subGenScopeArrays = nullptr;
+
 };
 
 class ModuleDefinitionFactory {

diff --git a/include/Surelog/DesignCompile/CompileHelper.h b/include/Surelog/DesignCompile/CompileHelper.h
@@ -429,12 +429,17 @@ class CompileHelper final {
                                     const FileContent* fC, NodeId nodeId,
                                     CompileDesign* compileDesign);
 
+  uint32_t getBuiltinType(VObjectType type);
+
   void compileLetDeclaration(DesignComponent* component, const FileContent* fC,
                              NodeId nodeId, CompileDesign* compileDesign);
 
   void compileInstantiation(ModuleDefinition* mod, const FileContent* fC,
                             CompileDesign* compileDesign, NodeId id,
                             ValuedComponentI* instance);
+  void compileGateInstantiation(ModuleDefinition* mod, const FileContent* fC,
+                            CompileDesign* compileDesign, NodeId id,
+                            ValuedComponentI* instance);
   void compileHighConn(ModuleDefinition* component, const FileContent* fC,
                        CompileDesign* compileDesign, NodeId id,
                        UHDM::VectorOfport* ports);

diff --git a/src/DesignCompile/CompileHelper.cpp b/src/DesignCompile/CompileHelper.cpp
@@ -2460,6 +2460,149 @@ void CompileHelper::compileInstantiation(ModuleDefinition* mod,
   }
 }
 
+uint32_t CompileHelper::getBuiltinType(VObjectType type) {
+  switch (type) {
+    case VObjectType::slNInpGate_And:
+      return vpiAndPrim;
+    case VObjectType::slNInpGate_Or:
+      return vpiOrPrim;
+    case VObjectType::slNInpGate_Nor:
+      return vpiNorPrim;
+    case VObjectType::slNInpGate_Nand:
+      return vpiNandPrim;
+    case VObjectType::slNInpGate_Xor:
+      return vpiXorPrim;
+    case VObjectType::slNInpGate_Xnor:
+      return vpiXnorPrim;
+    case VObjectType::slNOutGate_Buf:
+      return vpiBufPrim;
+    case VObjectType::slNOutGate_Not:
+      return vpiNotPrim;
+    case VObjectType::slPassEnSwitch_Tranif0:
+      return vpiTranif0Prim;
+    case VObjectType::slPassEnSwitch_Tranif1:
+      return vpiTranif1Prim;
+    case VObjectType::slPassEnSwitch_RTranif1:
+      return vpiRtranif1Prim;
+    case VObjectType::slPassEnSwitch_RTranif0:
+      return vpiRtranif0Prim;
+    case VObjectType::slPassSwitch_Tran:
+      return vpiTranPrim;
+    case VObjectType::slPassSwitch_RTran:
+      return vpiRtranPrim;
+    case VObjectType::slCmosSwitchType_Cmos:
+      return vpiCmosPrim;
+    case VObjectType::slCmosSwitchType_RCmos:
+      return vpiRcmosPrim;
+    case VObjectType::slEnableGateType_Bufif0:
+      return vpiBufif0Prim;
+    case VObjectType::slEnableGateType_Bufif1:
+      return vpiBufif1Prim;
+    case VObjectType::slEnableGateType_Notif0:
+      return vpiNotif0Prim;
+    case VObjectType::slEnableGateType_Notif1:
+      return vpiNotif1Prim;
+    case VObjectType::slMosSwitchType_NMos:
+      return vpiNmosPrim;
+    case VObjectType::slMosSwitchType_PMos:
+      return vpiPmosPrim;
+    case VObjectType::slMosSwitchType_RNMos:
+      return vpiRnmosPrim;
+    case VObjectType::slMosSwitchType_RPMos:
+      return vpiRpmosPrim;
+    case VObjectType::slPullup:
+      return vpiPullupPrim;
+    case VObjectType::slPulldown:
+      return vpiPulldownPrim;
+    default:
+      return 0;
+  }
+}
+
+void CompileHelper::compileGateInstantiation(ModuleDefinition* mod,
+                                             const FileContent* fC,
+                                             CompileDesign* compileDesign,
+                                             NodeId id,
+                                             ValuedComponentI* instance) {
+  UHDM::Serializer& s = compileDesign->getSerializer();
+  UHDM::primitive* gate = nullptr;
+  UHDM::primitive_array* gate_array = nullptr;
+  NodeId gatenode = fC->Child(fC->Parent(id));
+  VObjectType gatetype = fC->Type(gatenode);
+  int32_t vpiGateType = getBuiltinType(gatetype);
+  NodeId Name_of_instance = fC->Child(id);
+  NodeId Name = fC->Child(Name_of_instance);
+  NodeId Unpacked_dimension = fC->Sibling(Name);
+  if (vpiGateType == vpiPmosPrim || vpiGateType == vpiRpmosPrim ||
+      vpiGateType == vpiNmosPrim || vpiGateType == vpiRnmosPrim ||
+      vpiGateType == vpiCmosPrim || vpiGateType == vpiRcmosPrim ||
+      vpiGateType == vpiTranif1Prim || vpiGateType == vpiTranif0Prim ||
+      vpiGateType == vpiRtranif1Prim || vpiGateType == vpiRtranif0Prim ||
+      vpiGateType == vpiTranPrim || vpiGateType == vpiRtranPrim) {
+    gate = s.MakeSwitch_tran();
+    if (fC->Type(Unpacked_dimension) == VObjectType::slUnpacked_dimension) {
+      gate_array = s.MakeSwitch_array();
+      VectorOfprimitive* prims = s.MakePrimitiveVec();
+      int32_t size;
+      VectorOfrange* ranges =
+          compileRanges(mod, fC, Unpacked_dimension, compileDesign, nullptr,
+                        instance, false, size, false);
+      gate_array->Primitives(prims);
+      gate_array->Ranges(ranges);
+      prims->push_back(gate);
+      if (mod->getPrimitiveArrays() == nullptr) {
+        mod->setPrimitiveArrays(s.MakePrimitive_arrayVec());
+      }
+      mod->getPrimitiveArrays()->push_back(gate_array);
+    } else {
+      if (mod->getPrimitives() == nullptr) {
+        mod->setPrimitives(s.MakePrimitiveVec());
+      }
+      mod->getPrimitives()->push_back(gate);
+    }
+    gate->VpiPrimType(vpiGateType);
+  } else {
+    gate = s.MakeGate();
+    if (fC->Type(Unpacked_dimension) == VObjectType::slUnpacked_dimension) {
+      gate_array = s.MakeGate_array();
+      gate_array->VpiName(fC->SymName(Name));
+      fC->populateCoreMembers(id, id, gate_array);
+      VectorOfprimitive* prims = s.MakePrimitiveVec();
+      gate_array->Primitives(prims);
+      int32_t size;
+      VectorOfrange* ranges =
+          compileRanges(mod, fC, Unpacked_dimension, compileDesign, nullptr,
+                        instance, false, size, false);
+      gate_array->Ranges(ranges);
+      prims->push_back(gate);
+      if (mod->getPrimitiveArrays() == nullptr) {
+        mod->setPrimitiveArrays(s.MakePrimitive_arrayVec());
+      }
+      mod->getPrimitiveArrays()->push_back(gate_array);
+    } else {
+      if (mod->getPrimitives() == nullptr) {
+        mod->setPrimitives(s.MakePrimitiveVec());
+      }
+      mod->getPrimitives()->push_back(gate);
+    }
+
+    gate->VpiPrimType(vpiGateType);
+  }
+  /*
+  if (UHDM::VectorOfexpr* delays = child->getNetlist()->delays()) {
+    if (delays->size() == 1) {
+      gate->Delay((*delays)[0]);
+    }
+  }
+  */
+  if (gate) {
+    gate->VpiName(fC->SymName(Name));
+    // gate->VpiDefName(child->getModuleName());
+    fC->populateCoreMembers(id, id, gate);
+  }
+  // writePrimTerms(child, gate, vpiGateType, s);
+}
+
 void CompileHelper::compileHighConn(ModuleDefinition* component,
                                     const FileContent* fC,
                                     CompileDesign* compileDesign, NodeId instId,

diff --git a/src/DesignCompile/CompileModule.cpp b/src/DesignCompile/CompileModule.cpp
@@ -768,8 +768,6 @@ bool CompileModule::collectModuleObjects_(CollectType collectType) {
         }
         case VObjectType::slParam_assignment:
         case VObjectType::slHierarchical_instance:
-        case VObjectType::slN_input_gate_instance:
-        case VObjectType::slN_output_gate_instance:
         case VObjectType::slUdp_instance:
         case VObjectType::slUdp_instantiation:
         case VObjectType::slGate_instantiation:
@@ -785,6 +783,15 @@ bool CompileModule::collectModuleObjects_(CollectType collectType) {
           m_module->addObject(type, fnid);
           break;
         }
+        case VObjectType::slN_input_gate_instance:
+        case VObjectType::slN_output_gate_instance: {
+          if (collectType != CollectType::OTHER) break;
+          FileCNodeId fnid(fC, id);
+          m_module->addObject(type, fnid);
+          m_helper.compileGateInstantiation(m_module, fC, m_compileDesign, id,
+                                            m_instance);
+          break;
+        }
         case VObjectType::slInterface_instantiation:
         case VObjectType::slModule_instantiation:
         case VObjectType::slProgram_instantiation: {

diff --git a/src/DesignCompile/UhdmWriter.cpp b/src/DesignCompile/UhdmWriter.cpp
@@ -1229,17 +1229,30 @@ void UhdmWriter::writeModule(ModuleDefinition* mod, module_inst* m,
     }
   }
   // Module Instantiation
-
   if (std::vector<UHDM::ref_module*>* subModules = mod->getRefModules()) {
     m->Ref_modules(subModules);
+    for (auto subModArr : *subModules) {
+      subModArr->VpiParent(m);
+    }
   }
   if (VectorOfmodule_array* subModuleArrays = mod->getModuleArrays()) {
     m->Module_arrays(subModuleArrays);
     for (auto subModArr : *subModuleArrays) {
       subModArr->VpiParent(m);
     }
   }
-
+  if (UHDM::VectorOfprimitive* subModules = mod->getPrimitives()) {
+    m->Primitives(subModules);
+    for (auto subModArr : *subModules) {
+      subModArr->VpiParent(m);
+    }
+  }
+  if (UHDM::VectorOfprimitive_array* subModules = mod->getPrimitiveArrays()) {
+    m->Primitive_arrays(subModules);
+    for (auto subModArr : *subModules) {
+      subModArr->VpiParent(m);
+    }
+  }
   // Interface instantiation
   const std::vector<Signal*>& signals = mod->getSignals();
   if (!signals.empty()) {

diff --git a/tests/ArianeElab/ArianeElab.log b/tests/ArianeElab/ArianeElab.log
@@ -97155,6 +97155,8 @@ design: (work@top)
     \_package: ariane_pkg (ariane_pkg::), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:674:1, endln:1483:11
   |vpiRefModule:
   \_ref_module: work@ex_stage (ex_stage_i), line:2064:9, endln:2064:19
+    |vpiParent:
+    \_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2058:1, endln:2067:10
     |vpiName:ex_stage_i
     |vpiDefName:work@ex_stage
     |vpiActual:
@@ -107616,6 +107618,8 @@ design: (work@top)
   |vpiDefName:work@top
   |vpiRefModule:
   \_ref_module: work@ariane (i_ariane), line:2072:9, endln:2072:17
+    |vpiParent:
+    \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ArianeElab/dut.sv, line:2069:1, endln:2074:10
     |vpiName:i_ariane
     |vpiDefName:work@ariane
     |vpiActual:

diff --git a/tests/ArianeElab2/ArianeElab2.log b/tests/ArianeElab2/ArianeElab2.log
@@ -97787,6 +97787,8 @@ design: (work@top)
     \_package: ariane_pkg (ariane_pkg::), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:674:1, endln:1483:11
   |vpiRefModule:
   \_ref_module: work@ex_stage (ex_stage_i), line:2120:9, endln:2120:19
+    |vpiParent:
+    \_module_inst: work@ariane (work@ariane), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2114:1, endln:2123:10
     |vpiName:ex_stage_i
     |vpiDefName:work@ex_stage
     |vpiActual:
@@ -108539,6 +108541,8 @@ design: (work@top)
   |vpiDefName:work@top
   |vpiRefModule:
   \_ref_module: work@ariane (i_ariane), line:2128:9, endln:2128:17
+    |vpiParent:
+    \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/ArianeElab2/dut.sv, line:2125:1, endln:2130:10
     |vpiName:i_ariane
     |vpiDefName:work@ariane
     |vpiActual:

diff --git a/tests/ArrayExprFuncArg/ArrayExprFunArg.log b/tests/ArrayExprFuncArg/ArrayExprFunArg.log
@@ -657,6 +657,8 @@ design: (work@main)
   |vpiDefName:work@main
   |vpiRefModule:
   \_ref_module: work@top (top1), line:47:9, endln:47:13
+    |vpiParent:
+    \_module_inst: work@main (work@main), file:${SURELOG_DIR}/tests/ArrayExprFuncArg/dut.sv, line:46:1, endln:48:10
     |vpiName:top1
     |vpiDefName:work@top
     |vpiActual:

diff --git a/tests/AssignmentPatternInAssignmentPattern/AssignmentPatternInAssignmentPattern.log b/tests/AssignmentPatternInAssignmentPattern/AssignmentPatternInAssignmentPattern.log
@@ -2384,6 +2384,8 @@ design: (work@top)
   |vpiDefName:work@top
   |vpiRefModule:
   \_ref_module: work@foo (f), line:42:5, endln:42:6
+    |vpiParent:
+    \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/AssignmentPatternInAssignmentPattern/dut.sv, line:40:1, endln:44:10
     |vpiName:f
     |vpiDefName:work@foo
     |vpiActual:

diff --git a/tests/Attributes/Attributes.log b/tests/Attributes/Attributes.log
@@ -2144,6 +2144,8 @@ design: (work@foo)
       \_logic_net: ($37)
   |vpiRefModule:
   \_ref_module: work@bar (bar_instance), line:19:7, endln:19:19
+    |vpiParent:
+    \_module_inst: work@foo (work@foo), file:${SURELOG_DIR}/tests/Attributes/dut.sv, line:13:1, endln:41:10
     |vpiName:bar_instance
     |vpiDefName:work@bar
     |vpiActual:

diff --git a/tests/Attributes2/Attributes2.log b/tests/Attributes2/Attributes2.log
@@ -948,6 +948,8 @@ design: (work@foo)
     \_logic_typespec: , line:9:28, endln:9:32
   |vpiRefModule:
   \_ref_module: work@bar (bar_instance_1), line:11:7, endln:11:21
+    |vpiParent:
+    \_module_inst: work@foo (work@foo), file:${SURELOG_DIR}/tests/Attributes2/dut.sv, line:8:1, endln:12:10
     |vpiName:bar_instance_1
     |vpiDefName:work@bar
     |vpiActual:

diff --git a/tests/BindStmt/BindStmt.log b/tests/BindStmt/BindStmt.log
@@ -669,6 +669,8 @@ design: (work@testbench)
       \_logic_net: (a)
   |vpiRefModule:
   \_ref_module: work@sub (sub1), line:10:7, endln:10:11
+    |vpiParent:
+    \_module_inst: work@bp_me_nonsynth_lce_tracer (work@bp_me_nonsynth_lce_tracer), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:8:1, endln:11:10
     |vpiName:sub1
     |vpiDefName:work@sub
     |vpiActual:
@@ -781,6 +783,8 @@ design: (work@testbench)
       \_logic_net: ([email protected]_tracer2.a), line:13:75, endln:13:76
   |vpiRefModule:
   \_ref_module: work@sub (sub1), line:15:7, endln:15:11
+    |vpiParent:
+    \_module_inst: work@bp_me_nonsynth_lce_tracer2 (work@bp_me_nonsynth_lce_tracer2), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:13:1, endln:16:10
     |vpiName:sub1
     |vpiDefName:work@sub
     |vpiActual:
@@ -793,6 +797,8 @@ design: (work@testbench)
   |vpiDefName:work@inter
   |vpiRefModule:
   \_ref_module: work@bp_lce (u1), line:21:23, endln:21:25
+    |vpiParent:
+    \_module_inst: work@inter (work@inter), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:19:1, endln:23:10
     |vpiName:u1
     |vpiDefName:work@bp_lce
     |vpiActual:
@@ -853,12 +859,16 @@ design: (work@testbench)
     \_logic_typespec: , line:25:25, endln:25:30
   |vpiRefModule:
   \_ref_module: work@bp_lce (u1), line:27:24, endln:27:26
+    |vpiParent:
+    \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:25:1, endln:52:10
     |vpiName:u1
     |vpiDefName:work@bp_lce
     |vpiActual:
     \_module_inst: work@bp_lce (work@bp_lce), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:1:1, endln:3:10
   |vpiRefModule:
   \_ref_module: work@inter (tt), line:28:9, endln:28:11
+    |vpiParent:
+    \_module_inst: work@testbench (work@testbench), file:${SURELOG_DIR}/tests/BindStmt/dut.sv, line:25:1, endln:52:10
     |vpiName:tt
     |vpiDefName:work@inter
     |vpiActual:

diff --git a/tests/Bindings/Bindings.log b/tests/Bindings/Bindings.log
@@ -2790,12 +2790,16 @@ design: (work@dut1)
       \_logic_net: (lockup)
   |vpiRefModule:
   \_ref_module: work@bsg_dff_reset (a1), line:56:32, endln:56:34
+    |vpiParent:
+    \_module_inst: work@dut3 (work@dut3), file:${SURELOG_DIR}/tests/Bindings/dut.sv, line:54:1, endln:64:10
     |vpiName:a1
     |vpiDefName:work@bsg_dff_reset
     |vpiActual:
     \_module_inst: work@bsg_dff_reset (work@bsg_dff_reset), file:${SURELOG_DIR}/tests/Bindings/dut.sv, line:67:1, endln:80:10
   |vpiRefModule:
   \_ref_module: work@bsg_dff_reset (a2), line:58:17, endln:58:19
+    |vpiParent:
+    \_module_inst: work@dut3 (work@dut3), file:${SURELOG_DIR}/tests/Bindings/dut.sv, line:54:1, endln:64:10
     |vpiName:a2
     |vpiDefName:work@bsg_dff_reset
     |vpiActual:

diff --git a/tests/BitsArray/BitsArray.log b/tests/BitsArray/BitsArray.log
@@ -392,6 +392,8 @@ design: (work@top)
     |vpiNetType:36
   |vpiRefModule:
   \_ref_module: work@aes_reg_status (u_reg_status_key_init), line:17:6, endln:17:27
+    |vpiParent:
+    \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/BitsArray/dut.sv, line:9:1, endln:21:10
     |vpiName:u_reg_status_key_init
     |vpiDefName:work@aes_reg_status
     |vpiActual: