Merge pull request #3943 from alainmarcel/alainmarcel-patch-1

Alainmarcel patch 1

tests/UnboundForLoop/UnboundForLoop.log

@@ -496,6 +496,7 @@ design: (work@signed_shifter)
         \_case_stmt: 
           |vpiParent:
           \_begin: (work@signed_shifter), line:5:14, endln:7:6
+          |vpiCaseType:1
           |vpiCondition:
           \_ref_obj: (work@signed_shifter.i)
             |vpiParent:

third_party/tests/CoresSweRVMP/CoresSweRVMP.log

@@ -64,21 +64,21 @@ Running: cd ${SURELOG_DIR}/build/regression/CoresSweRVMP/slpp_all/mp_preprocess;
 -- Configuring done
 -- Generating done
 -- Build files have been written to: ${SURELOG_DIR}/build/regression/CoresSweRVMP/slpp_all/mp_preprocess
-[  6%] Generating 10_lsu_bus_intf.sv
-[ 12%] Generating 11_ifu_bp_ctl.sv
-[ 18%] Generating 12_beh_lib.sv
-[ 25%] Generating 13_ifu_mem_ctl.sv
-[ 31%] Generating 14_mem_lib.sv
-[ 37%] Generating 15_exu.sv
+[  6%] Generating 15_exu.sv
+[ 12%] Generating 10_lsu_bus_intf.sv
+[ 18%] Generating 13_ifu_mem_ctl.sv
+[ 25%] Generating 14_mem_lib.sv
+[ 31%] Generating 11_ifu_bp_ctl.sv
+[ 37%] Generating 12_beh_lib.sv
 [ 43%] Generating 16_dec_decode_ctl.sv
 [ 50%] Generating 1_lsu_stbuf.sv
 [ 56%] Generating 2_ahb_to_axi4.sv
 [ 62%] Generating 3_rvjtag_tap.sv
 [ 68%] Generating 4_dec_tlu_ctl.sv
 [ 75%] Generating 5_lsu_bus_buffer.sv
 [ 81%] Generating 6_dbg.sv
-[ 87%] Generating 7_axi4_to_ahb.sv
-[ 93%] Generating 8_ifu_aln_ctl.sv
+[ 87%] Generating 8_ifu_aln_ctl.sv
+[ 93%] Generating 7_axi4_to_ahb.sv
 [100%] Generating 9_tb_top.sv
 [100%] Built target Parse
 Surelog parsing status: 0