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Merge pull request #3977 from antmicro/bump-uhdm
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Bump third_party/UHDM
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@alaindargelas
alaindargelas authored Aug 6, 2024
2 parents 00df97c + f0524c0 commit ba2788a
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Showing 18 changed files with 487 additions and 479 deletions.
32 changes: 16 additions & 16 deletions tests/DashYTest/DashYTest.log
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Expand Up @@ -43,22 +43,6 @@ n<> u<11> t<Top_level_rule> c<1> l<1:1> el<3:1>
AST_DEBUG_END
AST_DEBUG_BEGIN
LIB: work
FILE: ${SURELOG_DIR}/tests/DashYTest/lib/OR.v
n<> u<0> t<_INVALID_> f<0> l<0:0>
n<> u<1> t<Null_rule> p<11> s<10> l<1:1> el<1:0>
n<module> u<2> t<Module_keyword> p<6> s<3> l<1:1> el<1:7>
n<OR> u<3> t<StringConst> p<6> s<5> l<1:8> el<1:10>
n<> u<4> t<Port> p<5> l<1:11> el<1:11>
n<> u<5> t<List_of_ports> p<6> c<4> l<1:10> el<1:12>
n<> u<6> t<Module_nonansi_header> p<8> c<2> s<7> l<1:1> el<1:13>
n<> u<7> t<ENDMODULE> p<8> l<2:1> el<2:10>
n<> u<8> t<Module_declaration> p<9> c<6> l<1:1> el<2:10>
n<> u<9> t<Description> p<10> c<8> l<1:1> el<2:10>
n<> u<10> t<Source_text> p<11> c<9> l<1:1> el<2:10>
n<> u<11> t<Top_level_rule> c<1> l<1:1> el<3:1>
AST_DEBUG_END
AST_DEBUG_BEGIN
LIB: work
FILE: ${SURELOG_DIR}/tests/DashYTest/lib/SIM.v
n<> u<0> t<_INVALID_> f<0> l<0:0>
n<> u<1> t<Null_rule> p<29> s<28> l<1:1> el<1:0>
Expand Down Expand Up @@ -91,6 +75,22 @@ n<> u<27> t<Description> p<28> c<26> l<1:1> el<6:10>
n<> u<28> t<Source_text> p<29> c<27> l<1:1> el<6:10>
n<> u<29> t<Top_level_rule> c<1> l<1:1> el<7:1>
AST_DEBUG_END
AST_DEBUG_BEGIN
LIB: work
FILE: ${SURELOG_DIR}/tests/DashYTest/lib/OR.v
n<> u<0> t<_INVALID_> f<0> l<0:0>
n<> u<1> t<Null_rule> p<11> s<10> l<1:1> el<1:0>
n<module> u<2> t<Module_keyword> p<6> s<3> l<1:1> el<1:7>
n<OR> u<3> t<StringConst> p<6> s<5> l<1:8> el<1:10>
n<> u<4> t<Port> p<5> l<1:11> el<1:11>
n<> u<5> t<List_of_ports> p<6> c<4> l<1:10> el<1:12>
n<> u<6> t<Module_nonansi_header> p<8> c<2> s<7> l<1:1> el<1:13>
n<> u<7> t<ENDMODULE> p<8> l<2:1> el<2:10>
n<> u<8> t<Module_declaration> p<9> c<6> l<1:1> el<2:10>
n<> u<9> t<Description> p<10> c<8> l<1:1> el<2:10>
n<> u<10> t<Source_text> p<11> c<9> l<1:1> el<2:10>
n<> u<11> t<Top_level_rule> c<1> l<1:1> el<3:1>
AST_DEBUG_END
[INF:CP0300] Compilation...
[INF:CP0303] ${SURELOG_DIR}/tests/DashYTest/lib/AND.v:1:1: Compile module "work@AND".
[INF:CP0303] ${SURELOG_DIR}/tests/DashYTest/lib/OR.v:1:1: Compile module "work@OR".
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8 changes: 2 additions & 6 deletions tests/HighLow/HighLow.log
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Original file line number Diff line number Diff line change
Expand Up @@ -298,7 +298,7 @@ AST_DEBUG_END
[INF:UH0706] Creating UHDM Model...
=== UHDM Object Stats Begin (Non-Elaborated Model) ===
begin 4
constant 42
constant 41
cont_assign 2
design 1
gen_if 4
Expand All @@ -320,7 +320,7 @@ sys_func_call 10
[INF:UH0707] Elaborating UHDM...
=== UHDM Object Stats Begin (Elaborated Model) ===
begin 4
constant 42
constant 41
cont_assign 3
design 1
gen_if 4
Expand Down Expand Up @@ -866,10 +866,7 @@ design: (work@top)
\_constant:
|vpiParent:
\_cont_assign: , line:12:10, endln:12:24
|vpiDecompile:2
|vpiSize:64
|UINT:2
|vpiConstType:9
|vpiLhs:
\_ref_obj: ([email protected]), line:12:10, endln:12:13
|vpiParent:
Expand Down Expand Up @@ -1064,7 +1061,6 @@ design: (work@top)
\_logic_typespec:
|vpiLeftRange:
\_constant:
|UINT:2
|vpiRightRange:
\_constant:
|UINT:1
Expand Down
14 changes: 7 additions & 7 deletions tests/LibraryIntercon/LibraryIntercon.log
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Original file line number Diff line number Diff line change
Expand Up @@ -6,31 +6,31 @@ LIB: work
${SURELOG_DIR}/tests/LibraryIntercon/lib.map

LIB: realLib
${SURELOG_DIR}/tests/LibraryIntercon/cmp.svr
${SURELOG_DIR}/tests/LibraryIntercon/driver.svr
${SURELOG_DIR}/tests/LibraryIntercon/cmp.svr

LIB: logicLib
${SURELOG_DIR}/tests/LibraryIntercon/driver.sv
${SURELOG_DIR}/tests/LibraryIntercon/cmp.sv
${SURELOG_DIR}/tests/LibraryIntercon/top.sv
${SURELOG_DIR}/tests/LibraryIntercon/cmp.sv


[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/tests/LibraryIntercon/nets.pkg".
[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/tests/LibraryIntercon/lib.map".
[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/tests/LibraryIntercon/cmp.svr".
[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/tests/LibraryIntercon/driver.svr".
[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/tests/LibraryIntercon/cmp.svr".
[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/tests/LibraryIntercon/driver.sv".
[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/tests/LibraryIntercon/cmp.sv".
[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/tests/LibraryIntercon/top.sv".
[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/tests/LibraryIntercon/cmp.sv".
[INF:PA0201] Parsing source file "${SURELOG_DIR}/tests/LibraryIntercon/nets.pkg".
[INF:PA0201] Parsing source file "${SURELOG_DIR}/tests/LibraryIntercon/cmp.svr".
[INF:PA0201] Parsing source file "${SURELOG_DIR}/tests/LibraryIntercon/driver.svr".
[INF:PA0201] Parsing source file "${SURELOG_DIR}/tests/LibraryIntercon/cmp.svr".
[INF:PA0201] Parsing source file "${SURELOG_DIR}/tests/LibraryIntercon/driver.sv".
[INF:PA0201] Parsing source file "${SURELOG_DIR}/tests/LibraryIntercon/cmp.sv".
[INF:PA0201] Parsing source file "${SURELOG_DIR}/tests/LibraryIntercon/top.sv".
[INF:PA0201] Parsing source file "${SURELOG_DIR}/tests/LibraryIntercon/cmp.sv".
[WRN:PA0205] ${SURELOG_DIR}/tests/LibraryIntercon/nets.pkg:1:1: No timescale set for "NetsPkg".
[WRN:PA0205] ${SURELOG_DIR}/tests/LibraryIntercon/cmp.sv:2:1: No timescale set for "cmp".
[WRN:PA0205] ${SURELOG_DIR}/tests/LibraryIntercon/top.sv:1:1: No timescale set for "top".
[WRN:PA0205] ${SURELOG_DIR}/tests/LibraryIntercon/cmp.sv:2:1: No timescale set for "cmp".
[INF:CP0300] Compilation...
[INF:CP0301] ${SURELOG_DIR}/tests/LibraryIntercon/nets.pkg:1:1: Compile package "NetsPkg".
[INF:CP0303] ${SURELOG_DIR}/tests/LibraryIntercon/cmp.sv:2:1: Compile module "logicLib@cmp".
Expand Down
32 changes: 16 additions & 16 deletions tests/NonSynthUnusedMod/NonSynthUnusedMod.log
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Expand Up @@ -27,22 +27,6 @@ n<> u<21> t<Top_level_rule> c<1> l<1:1> el<8:1>
AST_DEBUG_END
AST_DEBUG_BEGIN
LIB: work
FILE: ${SURELOG_DIR}/tests/NonSynthUnusedMod/top.v
n<> u<0> t<_INVALID_> f<0> l<0:0>
n<> u<1> t<Null_rule> p<11> s<10> l<1:1> el<1:0>
n<module> u<2> t<Module_keyword> p<6> s<3> l<1:1> el<1:7>
n<top> u<3> t<StringConst> p<6> s<5> l<1:8> el<1:11>
n<> u<4> t<Port> p<5> l<1:12> el<1:12>
n<> u<5> t<List_of_ports> p<6> c<4> l<1:11> el<1:13>
n<> u<6> t<Module_nonansi_header> p<8> c<2> s<7> l<1:1> el<1:14>
n<> u<7> t<ENDMODULE> p<8> l<3:1> el<3:10>
n<> u<8> t<Module_declaration> p<9> c<6> l<1:1> el<3:10>
n<> u<9> t<Description> p<10> c<8> l<1:1> el<3:10>
n<> u<10> t<Source_text> p<11> c<9> l<1:1> el<3:10>
n<> u<11> t<Top_level_rule> c<1> l<1:1> el<4:1>
AST_DEBUG_END
AST_DEBUG_BEGIN
LIB: work
FILE: ${SURELOG_DIR}/tests/NonSynthUnusedMod/nonsynth.v
n<> u<0> t<_INVALID_> f<0> l<0:0>
n<> u<1> t<Null_rule> p<38> s<37> l<1:1> el<1:0>
Expand Down Expand Up @@ -84,6 +68,22 @@ n<> u<36> t<Description> p<37> c<35> l<1:1> el<7:10>
n<> u<37> t<Source_text> p<38> c<36> l<1:1> el<7:10>
n<> u<38> t<Top_level_rule> c<1> l<1:1> el<8:1>
AST_DEBUG_END
AST_DEBUG_BEGIN
LIB: work
FILE: ${SURELOG_DIR}/tests/NonSynthUnusedMod/top.v
n<> u<0> t<_INVALID_> f<0> l<0:0>
n<> u<1> t<Null_rule> p<11> s<10> l<1:1> el<1:0>
n<module> u<2> t<Module_keyword> p<6> s<3> l<1:1> el<1:7>
n<top> u<3> t<StringConst> p<6> s<5> l<1:8> el<1:11>
n<> u<4> t<Port> p<5> l<1:12> el<1:12>
n<> u<5> t<List_of_ports> p<6> c<4> l<1:11> el<1:13>
n<> u<6> t<Module_nonansi_header> p<8> c<2> s<7> l<1:1> el<1:14>
n<> u<7> t<ENDMODULE> p<8> l<3:1> el<3:10>
n<> u<8> t<Module_declaration> p<9> c<6> l<1:1> el<3:10>
n<> u<9> t<Description> p<10> c<8> l<1:1> el<3:10>
n<> u<10> t<Source_text> p<11> c<9> l<1:1> el<3:10>
n<> u<11> t<Top_level_rule> c<1> l<1:1> el<4:1>
AST_DEBUG_END
[INF:CP0300] Compilation...
[INF:CP0303] ${SURELOG_DIR}/tests/NonSynthUnusedMod/dut.sv:1:1: Compile module "work@dut".
[INF:CP0303] ${SURELOG_DIR}/tests/NonSynthUnusedMod/nonsynth.v:1:1: Compile module "work@nonsynth".
Expand Down
6 changes: 3 additions & 3 deletions tests/OldLibrary/OldLibrary.log
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Original file line number Diff line number Diff line change
@@ -1,16 +1,16 @@
[INF:CM0023] Creating log file "${SURELOG_DIR}/build/regression/OldLibrary/slpp_all/surelog.log".
[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/tests/OldLibrary/top.v".
[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/tests/OldLibrary/lib/CELL3.v".
[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/tests/OldLibrary/lib/CELL2.v".
[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/tests/OldLibrary/lib/CELL1.v".
[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/tests/OldLibrary/lib/CELL3.v".
[INF:PA0201] Parsing source file "${SURELOG_DIR}/tests/OldLibrary/top.v".
[INF:PA0201] Parsing source file "${SURELOG_DIR}/tests/OldLibrary/lib/CELL3.v".
[INF:PA0201] Parsing source file "${SURELOG_DIR}/tests/OldLibrary/lib/CELL2.v".
[INF:PA0201] Parsing source file "${SURELOG_DIR}/tests/OldLibrary/lib/CELL1.v".
[INF:PA0201] Parsing source file "${SURELOG_DIR}/tests/OldLibrary/lib/CELL3.v".
[WRN:PA0205] ${SURELOG_DIR}/tests/OldLibrary/top.v:1:1: No timescale set for "top".
[WRN:PA0205] ${SURELOG_DIR}/tests/OldLibrary/lib/CELL3.v:1:1: No timescale set for "CELL3".
[WRN:PA0205] ${SURELOG_DIR}/tests/OldLibrary/lib/CELL2.v:1:1: No timescale set for "CELL2".
[WRN:PA0205] ${SURELOG_DIR}/tests/OldLibrary/lib/CELL1.v:1:1: No timescale set for "CELL1".
[WRN:PA0205] ${SURELOG_DIR}/tests/OldLibrary/lib/CELL3.v:1:1: No timescale set for "CELL3".
[INF:CP0300] Compilation...
[INF:CP0303] ${SURELOG_DIR}/tests/OldLibrary/lib/CELL1.v:1:1: Compile module "work@CELL1".
[INF:CP0305] ${SURELOG_DIR}/tests/OldLibrary/lib/CELL2.v:1:1: Compile udp "work@CELL2".
Expand Down
60 changes: 30 additions & 30 deletions tests/PreprocLine/PreprocLine.log
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Original file line number Diff line number Diff line change
Expand Up @@ -13,38 +13,38 @@ n<top> u<3> t<StringConst> p<4> l<1:8> el<1:11>
n<> u<4> t<Module_ansi_header> p<66> c<2> s<64> l<1:1> el<1:12>
n<> u<5> t<Dollar_keyword> p<17> s<6> l<3:9> el<3:10>
n<display> u<6> t<StringConst> p<17> s<16> l<3:10> el<3:17>
n<"${SURELOG_DIR}/tests/PreprocLine/dut.sv"> u<7> t<StringLiteral> p<8> l<3:18> el<3:64>
n<> u<8> t<Primary_literal> p<9> c<7> l<3:18> el<3:64>
n<> u<9> t<Primary> p<10> c<8> l<3:18> el<3:64>
n<> u<10> t<Expression> p<16> c<9> s<15> l<3:18> el<3:64>
n<3> u<11> t<IntConst> p<12> l<3:66> el<3:67>
n<> u<12> t<Primary_literal> p<13> c<11> l<3:66> el<3:67>
n<> u<13> t<Primary> p<14> c<12> l<3:66> el<3:67>
n<> u<14> t<Expression> p<15> c<13> l<3:66> el<3:67>
n<> u<15> t<Argument> p<16> c<14> l<3:66> el<3:67>
n<> u<16> t<List_of_arguments> p<17> c<10> l<3:18> el<3:67>
n<> u<17> t<Subroutine_call> p<18> c<5> l<3:9> el<3:68>
n<> u<18> t<Subroutine_call_statement> p<19> c<17> l<3:9> el<3:69>
n<> u<19> t<Statement_item> p<20> c<18> l<3:9> el<3:69>
n<> u<20> t<Statement> p<21> c<19> l<3:9> el<3:69>
n<> u<21> t<Statement_or_null> p<57> c<20> s<38> l<3:9> el<3:69>
n<"${SURELOG_DIR}/tests/PreprocLine/dut.sv"> u<7> t<StringLiteral> p<8> l<3:18> el<3:91>
n<> u<8> t<Primary_literal> p<9> c<7> l<3:18> el<3:91>
n<> u<9> t<Primary> p<10> c<8> l<3:18> el<3:91>
n<> u<10> t<Expression> p<16> c<9> s<15> l<3:18> el<3:91>
n<3> u<11> t<IntConst> p<12> l<3:93> el<3:94>
n<> u<12> t<Primary_literal> p<13> c<11> l<3:93> el<3:94>
n<> u<13> t<Primary> p<14> c<12> l<3:93> el<3:94>
n<> u<14> t<Expression> p<15> c<13> l<3:93> el<3:94>
n<> u<15> t<Argument> p<16> c<14> l<3:93> el<3:94>
n<> u<16> t<List_of_arguments> p<17> c<10> l<3:18> el<3:94>
n<> u<17> t<Subroutine_call> p<18> c<5> l<3:9> el<3:95>
n<> u<18> t<Subroutine_call_statement> p<19> c<17> l<3:9> el<3:96>
n<> u<19> t<Statement_item> p<20> c<18> l<3:9> el<3:96>
n<> u<20> t<Statement> p<21> c<19> l<3:9> el<3:96>
n<> u<21> t<Statement_or_null> p<57> c<20> s<38> l<3:9> el<3:96>
n<> u<22> t<Dollar_keyword> p<34> s<23> l<5:9> el<5:10>
n<display> u<23> t<StringConst> p<34> s<33> l<5:10> el<5:17>
n<"${SURELOG_DIR}/tests/PreprocLine/fake.v"> u<24> t<StringLiteral> p<25> l<5:18> el<5:64>
n<> u<25> t<Primary_literal> p<26> c<24> l<5:18> el<5:64>
n<> u<26> t<Primary> p<27> c<25> l<5:18> el<5:64>
n<> u<27> t<Expression> p<33> c<26> s<32> l<5:18> el<5:64>
n<102> u<28> t<IntConst> p<29> l<5:66> el<5:69>
n<> u<29> t<Primary_literal> p<30> c<28> l<5:66> el<5:69>
n<> u<30> t<Primary> p<31> c<29> l<5:66> el<5:69>
n<> u<31> t<Expression> p<32> c<30> l<5:66> el<5:69>
n<> u<32> t<Argument> p<33> c<31> l<5:66> el<5:69>
n<> u<33> t<List_of_arguments> p<34> c<27> l<5:18> el<5:69>
n<> u<34> t<Subroutine_call> p<35> c<22> l<5:9> el<5:70>
n<> u<35> t<Subroutine_call_statement> p<36> c<34> l<5:9> el<5:71>
n<> u<36> t<Statement_item> p<37> c<35> l<5:9> el<5:71>
n<> u<37> t<Statement> p<38> c<36> l<5:9> el<5:71>
n<> u<38> t<Statement_or_null> p<57> c<37> s<55> l<5:9> el<5:71>
n<"${SURELOG_DIR}/tests/PreprocLine/fake.v"> u<24> t<StringLiteral> p<25> l<5:18> el<5:91>
n<> u<25> t<Primary_literal> p<26> c<24> l<5:18> el<5:91>
n<> u<26> t<Primary> p<27> c<25> l<5:18> el<5:91>
n<> u<27> t<Expression> p<33> c<26> s<32> l<5:18> el<5:91>
n<102> u<28> t<IntConst> p<29> l<5:93> el<5:96>
n<> u<29> t<Primary_literal> p<30> c<28> l<5:93> el<5:96>
n<> u<30> t<Primary> p<31> c<29> l<5:93> el<5:96>
n<> u<31> t<Expression> p<32> c<30> l<5:93> el<5:96>
n<> u<32> t<Argument> p<33> c<31> l<5:93> el<5:96>
n<> u<33> t<List_of_arguments> p<34> c<27> l<5:18> el<5:96>
n<> u<34> t<Subroutine_call> p<35> c<22> l<5:9> el<5:97>
n<> u<35> t<Subroutine_call_statement> p<36> c<34> l<5:9> el<5:98>
n<> u<36> t<Statement_item> p<37> c<35> l<5:9> el<5:98>
n<> u<37> t<Statement> p<38> c<36> l<5:9> el<5:98>
n<> u<38> t<Statement_or_null> p<57> c<37> s<55> l<5:9> el<5:98>
n<> u<39> t<Dollar_keyword> p<51> s<40> f<0> l<10:9> el<10:10>
n<display> u<40> t<StringConst> p<51> s<50> f<0> l<10:10> el<10:17>
n<""> u<41> t<StringLiteral> p<42> f<0> l<10:18> el<10:20>
Expand Down
6 changes: 3 additions & 3 deletions tests/TestSepCompNoHash/TestSepCompNoHash.log
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Original file line number Diff line number Diff line change
Expand Up @@ -20,15 +20,15 @@
[WARNING] : 1
[ NOTE] : 0
[INF:CM0023] Creating log file "${SURELOG_DIR}/tests/TestSepCompNoHash/slpp_all/surelog.log".
PP CACHE USED FOR: ${SURELOG_DIR}/tests/TestSepCompNoHash/top.sv
PP CACHE USED FOR: ${SURELOG_DIR}/tests/TestSepCompNoHash/pkg1.sv
PP CACHE USED FOR: ${SURELOG_DIR}/tests/TestSepCompNoHash/pkg2.sv
PARSER CACHE USED FOR: ${SURELOG_DIR}/tests/TestSepCompNoHash/top.sv
PP CACHE USED FOR: ${SURELOG_DIR}/tests/TestSepCompNoHash/top.sv
PARSER CACHE USED FOR: ${SURELOG_DIR}/tests/TestSepCompNoHash/pkg1.sv
PARSER CACHE USED FOR: ${SURELOG_DIR}/tests/TestSepCompNoHash/pkg2.sv
[WRN:PA0205] ${SURELOG_DIR}/tests/TestSepCompNoHash/top.sv:1:1: No timescale set for "top".
PARSER CACHE USED FOR: ${SURELOG_DIR}/tests/TestSepCompNoHash/top.sv
[WRN:PA0205] ${SURELOG_DIR}/tests/TestSepCompNoHash/pkg1.sv:1:1: No timescale set for "pkg1".
[WRN:PA0205] ${SURELOG_DIR}/tests/TestSepCompNoHash/pkg2.sv:1:1: No timescale set for "pkg2".
[WRN:PA0205] ${SURELOG_DIR}/tests/TestSepCompNoHash/top.sv:1:1: No timescale set for "top".
[INF:CP0300] Compilation...
[INF:CP0301] ${SURELOG_DIR}/tests/TestSepCompNoHash/pkg1.sv:1:1: Compile package "pkg1".
[INF:CP0301] ${SURELOG_DIR}/tests/TestSepCompNoHash/pkg2.sv:1:1: Compile package "pkg2".
Expand Down
6 changes: 3 additions & 3 deletions tests/UnitLibrary/UnitLibrary.log
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Original file line number Diff line number Diff line change
Expand Up @@ -22,8 +22,8 @@ LIB: lib1
${SURELOG_DIR}/tests/UnitLibrary/lib1/bot.sv

LIB: lib2
${SURELOG_DIR}/tests/UnitLibrary/lib2/sub.v
${SURELOG_DIR}/tests/UnitLibrary/lib2/bot.sv
${SURELOG_DIR}/tests/UnitLibrary/lib2/sub.v

LIB: lib3
${SURELOG_DIR}/tests/UnitLibrary/lib3/sub.v
Expand All @@ -49,8 +49,8 @@ LIB: libw
[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/tests/UnitLibrary/rtl/adder.v".
[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/tests/UnitLibrary/gate/adder.vg".
[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/tests/UnitLibrary/lib1/bot.sv".
[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/tests/UnitLibrary/lib2/sub.v".
[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/tests/UnitLibrary/lib2/bot.sv".
[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/tests/UnitLibrary/lib2/sub.v".
[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/tests/UnitLibrary/lib3/sub.v".
[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/tests/UnitLibrary/libwconfig/libw1/wsub.v".
[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/tests/UnitLibrary/libwconfig/libw2/wsub.v".
Expand All @@ -61,8 +61,8 @@ LIB: libw
[INF:PA0201] Parsing source file "${SURELOG_DIR}/tests/UnitLibrary/rtl/adder.v".
[INF:PA0201] Parsing source file "${SURELOG_DIR}/tests/UnitLibrary/gate/adder.vg".
[INF:PA0201] Parsing source file "${SURELOG_DIR}/tests/UnitLibrary/lib1/bot.sv".
[INF:PA0201] Parsing source file "${SURELOG_DIR}/tests/UnitLibrary/lib2/sub.v".
[INF:PA0201] Parsing source file "${SURELOG_DIR}/tests/UnitLibrary/lib2/bot.sv".
[INF:PA0201] Parsing source file "${SURELOG_DIR}/tests/UnitLibrary/lib2/sub.v".
[INF:PA0201] Parsing source file "${SURELOG_DIR}/tests/UnitLibrary/lib3/sub.v".
[INF:PA0201] Parsing source file "${SURELOG_DIR}/tests/UnitLibrary/libwconfig/libw1/wsub.v".
[INF:PA0201] Parsing source file "${SURELOG_DIR}/tests/UnitLibrary/libwconfig/libw2/wsub.v".
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2 changes: 1 addition & 1 deletion third_party/UHDM
Submodule UHDM updated 4 files
+2 −0 CMakeLists.txt
+9 −4 python/CMakeLists.txt
+6 −6 templates/ExprEval.cpp
+1 −0 templates/vpi_visitor.cpp
2 changes: 1 addition & 1 deletion third_party/tests/AzadiRTL/AzadiRTL.log
View file
Original file line number Diff line number Diff line change
Expand Up @@ -13904,7 +13904,7 @@ case_stmt 316
class_defn 8
class_typespec 4
class_var 3
constant 275929
constant 275928
cont_assign 15432
delay_control 8
design 1
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