Merge pull request #3914 from alainmarcel/alainmarcel-patch-1

top level param check
chipsalliance · Oct 25, 2023 · c742271 · c742271
2 parents b76a429 + 70a879f
commit c742271
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Showing 8 changed files with 241 additions and 10 deletions.
diff --git a/include/Surelog/ErrorReporting/ErrorDefinition.h b/include/Surelog/ErrorReporting/ErrorDefinition.h
@@ -246,6 +246,7 @@ class ErrorDefinition {
     ELAB_SYSTEM_WARNING = 548,
     ELAB_SYSTEM_INFO = 549,
     ELAB_UNKNOWN_PORT = 550,
+    ELAB_TOP_PARAMETER_NO_DEFAULT = 551,
     LIB_FILE_MAPS_TO_MULTIPLE_LIBS = 600,
     UHDM_UNSUPPORTED_EXPR = 700,
     UHDM_UNSUPPORTED_STMT = 701,

diff --git a/src/DesignCompile/DesignElaboration.cpp b/src/DesignCompile/DesignElaboration.cpp
@@ -2330,6 +2330,18 @@ std::vector<std::string_view> DesignElaboration::collectParams_(
           exprId = param.fC->Sibling(exprId);
         }
         NodeId Data_type = param.fC->Child(exprId);
+        if (instance->getParent() == nullptr) {
+          // Top level
+          if (exprId == InvalidNodeId) {
+            Location loc(param.fC->getFileId(ident), param.fC->Line(ident),
+                         param.fC->Column(ident),
+                         m_compileDesign->getCompiler()
+                             ->getSymbolTable()
+                             ->registerSymbol(name));
+            Error err(ErrorDefinition::ELAB_TOP_PARAMETER_NO_DEFAULT, loc);
+            m_compileDesign->getCompiler()->getErrorContainer()->addError(err);
+          }
+        }
         if (param.fC->Type(Data_type) != VObjectType::paData_type) {
           // Regular params
           Parameter* p = module->getParameter(name);

diff --git a/src/ErrorReporting/ErrorDefinition.cpp b/src/ErrorReporting/ErrorDefinition.cpp
@@ -427,6 +427,8 @@ bool ErrorDefinition::init() {
   rec(ELAB_INVALID_CASE_STMT_VALUE, ERROR, ELAB,
       "Invalid generate case stmt value");
   rec(ELAB_UNKNOWN_PORT, ERROR, ELAB, "Unknown port \"%s\"");
+  rec(ELAB_TOP_PARAMETER_NO_DEFAULT, ERROR, ELAB,
+      "Top-level parameter with no default value \"%s\"");
   rec(ELAB_SYSTEM_FATAL, FATAL, ELAB, "Fatal elaboration %s");
   rec(ELAB_SYSTEM_ERROR, ERROR, ELAB, "Elaboration error %s");
   rec(ELAB_SYSTEM_WARNING, WARNING, ELAB, "Elaboration warning %s");

diff --git a/tests/TopParam/TopParam.log b/tests/TopParam/TopParam.log
@@ -0,0 +1,198 @@
+[INF:CM0023] Creating log file "${SURELOG_DIR}/build/regression/TopParam/slpp_all/surelog.log".
+AST_DEBUG_BEGIN
+LIB:  work
+FILE: ${SURELOG_DIR}/tests/TopParam/dut.sv
+n<> u<0> t<_INVALID_> f<0> l<0:0>
+n<> u<1> t<Null_rule> p<50> s<49> l<1:1> el<1:0>
+n<module> u<2> t<Module_keyword> p<11> s<3> l<1:1> el<1:7>
+n<top> u<3> t<StringConst> p<11> s<10> l<1:8> el<1:11>
+n<> u<4> t<Data_type_or_implicit> p<8> s<7> l<2:15> el<2:15>
+n<param> u<5> t<StringConst> p<6> l<2:15> el<2:20>
+n<> u<6> t<Param_assignment> p<7> c<5> l<2:15> el<2:20>
+n<> u<7> t<List_of_param_assignments> p<8> c<6> l<2:15> el<2:20>
+n<> u<8> t<Parameter_declaration> p<9> c<4> l<2:5> el<2:20>
+n<> u<9> t<Parameter_port_declaration> p<10> c<8> l<2:5> el<2:20>
+n<> u<10> t<Parameter_port_list> p<11> c<9> l<1:12> el<3:2>
+n<> u<11> t<Module_ansi_header> p<32> c<2> s<30> l<1:1> el<3:3>
+n<test> u<12> t<StringConst> p<28> s<22> l<5:5> el<5:9>
+n<param> u<13> t<StringConst> p<20> s<19> l<6:10> el<6:15>
+n<param> u<14> t<StringConst> p<15> l<6:16> el<6:21>
+n<> u<15> t<Primary_literal> p<16> c<14> l<6:16> el<6:21>
+n<> u<16> t<Primary> p<17> c<15> l<6:16> el<6:21>
+n<> u<17> t<Expression> p<18> c<16> l<6:16> el<6:21>
+n<> u<18> t<Mintypmax_expression> p<19> c<17> l<6:16> el<6:21>
+n<> u<19> t<Param_expression> p<20> c<18> l<6:16> el<6:21>
+n<> u<20> t<Named_parameter_assignment> p<21> c<13> l<6:9> el<6:22>
+n<> u<21> t<List_of_parameter_assignments> p<22> c<20> l<6:9> el<6:22>
+n<> u<22> t<Parameter_value_assignment> p<28> c<21> s<27> l<5:10> el<7:6>
+n<test_i> u<23> t<StringConst> p<24> l<7:7> el<7:13>
+n<> u<24> t<Name_of_instance> p<27> c<23> s<26> l<7:7> el<7:13>
+n<> u<25> t<Ordered_port_connection> p<26> l<8:5> el<7:20>
+n<> u<26> t<List_of_port_connections> p<27> c<25> l<8:5> el<7:20>
+n<> u<27> t<Hierarchical_instance> p<28> c<24> l<7:7> el<8:6>
+n<> u<28> t<Module_instantiation> p<29> c<12> l<5:5> el<8:7>
+n<> u<29> t<Module_or_generate_item> p<30> c<28> l<5:5> el<8:7>
+n<> u<30> t<Non_port_module_item> p<32> c<29> s<31> l<5:5> el<8:7>
+n<> u<31> t<ENDMODULE> p<32> l<10:1> el<10:10>
+n<> u<32> t<Module_declaration> p<33> c<11> l<1:1> el<10:10>
+n<> u<33> t<Description> p<49> c<32> s<48> l<1:1> el<10:10>
+n<module> u<34> t<Module_keyword> p<45> s<35> l<12:1> el<12:7>
+n<test> u<35> t<StringConst> p<45> s<42> l<12:8> el<12:12>
+n<> u<36> t<Data_type_or_implicit> p<40> s<39> l<13:15> el<13:15>
+n<param> u<37> t<StringConst> p<38> l<13:15> el<13:20>
+n<> u<38> t<Param_assignment> p<39> c<37> l<13:15> el<13:20>
+n<> u<39> t<List_of_param_assignments> p<40> c<38> l<13:15> el<13:20>
+n<> u<40> t<Parameter_declaration> p<41> c<36> l<13:5> el<13:20>
+n<> u<41> t<Parameter_port_declaration> p<42> c<40> l<13:5> el<13:20>
+n<> u<42> t<Parameter_port_list> p<45> c<41> s<44> l<12:13> el<14:2>
+n<> u<43> t<Port> p<44> l<14:3> el<14:3>
+n<> u<44> t<List_of_ports> p<45> c<43> l<14:2> el<14:4>
+n<> u<45> t<Module_nonansi_header> p<47> c<34> s<46> l<12:1> el<14:5>
+n<> u<46> t<ENDMODULE> p<47> l<16:1> el<16:10>
+n<> u<47> t<Module_declaration> p<48> c<45> l<12:1> el<16:10>
+n<> u<48> t<Description> p<49> c<47> l<12:1> el<16:10>
+n<> u<49> t<Source_text> p<50> c<33> l<1:1> el<16:10>
+n<> u<50> t<Top_level_rule> c<1> l<1:1> el<17:1>
+AST_DEBUG_END
+[WRN:PA0205] ${SURELOG_DIR}/tests/TopParam/dut.sv:1:1: No timescale set for "top".
+[WRN:PA0205] ${SURELOG_DIR}/tests/TopParam/dut.sv:12:1: No timescale set for "test".
+[INF:CP0300] Compilation...
+[INF:CP0303] ${SURELOG_DIR}/tests/TopParam/dut.sv:12:1: Compile module "work@test".
+[INF:CP0303] ${SURELOG_DIR}/tests/TopParam/dut.sv:1:1: Compile module "work@top".
+[INF:EL0526] Design Elaboration...
+[NTE:EL0503] ${SURELOG_DIR}/tests/TopParam/dut.sv:1:1: Top level module "work@top".
+[ERR:EL0551] ${SURELOG_DIR}/tests/TopParam/dut.sv:2:15: Top-level parameter with no default value "param".
+[NTE:EL0508] Nb Top level modules: 1.
+[NTE:EL0509] Max instance depth: 2.
+[NTE:EL0510] Nb instances: 2.
+[NTE:EL0511] Nb leaf instances: 1.
+[INF:UH0706] Creating UHDM Model...
+=== UHDM Object Stats Begin (Non-Elaborated Model) ===
+design                                                 1
+module_inst                                            6
+param_assign                                           4
+parameter                                              4
+ref_module                                             1
+ref_obj                                                1
+=== UHDM Object Stats End ===
+[INF:UH0707] Elaborating UHDM...
+=== UHDM Object Stats Begin (Elaborated Model) ===
+design                                                 1
+module_inst                                            6
+param_assign                                           4
+parameter                                              4
+ref_module                                             1
+ref_obj                                                1
+=== UHDM Object Stats End ===
+[INF:UH0708] Writing UHDM DB: ${SURELOG_DIR}/build/regression/TopParam/slpp_all/surelog.uhdm ...
+[INF:UH0709] Writing UHDM Html Coverage: ${SURELOG_DIR}/build/regression/TopParam/slpp_all/checker/surelog.chk.html ...
+[INF:UH0710] Loading UHDM DB: ${SURELOG_DIR}/build/regression/TopParam/slpp_all/surelog.uhdm ...
+[INF:UH0711] Decompiling UHDM...
+====== UHDM =======
+design: (work@top)
+|vpiElaborated:1
+|vpiName:work@top
+|uhdmallModules:
+\_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/TopParam/dut.sv, line:12:1, endln:16:10
+  |vpiParent:
+  \_design: (work@top)
+  |vpiFullName:work@test
+  |vpiParameter:
+  \_parameter: ([email protected]), line:13:15, endln:13:20
+    |vpiParent:
+    \_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/TopParam/dut.sv, line:12:1, endln:16:10
+    |vpiName:param
+    |vpiFullName:[email protected]
+  |vpiParamAssign:
+  \_param_assign: , line:13:15, endln:13:20
+    |vpiParent:
+    \_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/TopParam/dut.sv, line:12:1, endln:16:10
+    |vpiLhs:
+    \_parameter: ([email protected]), line:13:15, endln:13:20
+  |vpiDefName:work@test
+|uhdmallModules:
+\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/TopParam/dut.sv, line:1:1, endln:10:10
+  |vpiParent:
+  \_design: (work@top)
+  |vpiFullName:work@top
+  |vpiParameter:
+  \_parameter: ([email protected]), line:2:15, endln:2:20
+    |vpiParent:
+    \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/TopParam/dut.sv, line:1:1, endln:10:10
+    |vpiName:param
+    |vpiFullName:[email protected]
+  |vpiParamAssign:
+  \_param_assign: , line:2:15, endln:2:20
+    |vpiParent:
+    \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/TopParam/dut.sv, line:1:1, endln:10:10
+    |vpiLhs:
+    \_parameter: ([email protected]), line:2:15, endln:2:20
+  |vpiDefName:work@top
+  |vpiRefModule:
+  \_ref_module: work@test (test_i), line:7:7, endln:7:13
+    |vpiParent:
+    \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/TopParam/dut.sv, line:1:1, endln:10:10
+    |vpiName:test_i
+    |vpiDefName:work@test
+    |vpiActual:
+    \_module_inst: work@test (work@test), file:${SURELOG_DIR}/tests/TopParam/dut.sv, line:12:1, endln:16:10
+|uhdmtopModules:
+\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/TopParam/dut.sv, line:1:1, endln:10:10
+  |vpiName:work@top
+  |vpiParameter:
+  \_parameter: ([email protected]), line:2:15, endln:2:20
+    |vpiParent:
+    \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/TopParam/dut.sv, line:1:1, endln:10:10
+    |vpiName:param
+    |vpiFullName:[email protected]
+  |vpiParamAssign:
+  \_param_assign: , line:2:15, endln:2:20
+    |vpiParent:
+    \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/TopParam/dut.sv, line:1:1, endln:10:10
+    |vpiLhs:
+    \_parameter: ([email protected]), line:2:15, endln:2:20
+  |vpiDefName:work@top
+  |vpiTop:1
+  |vpiTopModule:1
+  |vpiModule:
+  \_module_inst: work@test ([email protected]_i), file:${SURELOG_DIR}/tests/TopParam/dut.sv, line:5:5, endln:8:7
+    |vpiParent:
+    \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/TopParam/dut.sv, line:1:1, endln:10:10
+    |vpiName:test_i
+    |vpiFullName:[email protected]_i
+    |vpiParameter:
+    \_parameter: ([email protected]_i.param), line:13:15, endln:13:20
+      |vpiParent:
+      \_module_inst: work@test ([email protected]_i), file:${SURELOG_DIR}/tests/TopParam/dut.sv, line:5:5, endln:8:7
+      |vpiName:param
+      |vpiFullName:[email protected]_i.param
+    |vpiParamAssign:
+    \_param_assign: , line:13:15, endln:13:20
+      |vpiParent:
+      \_module_inst: work@test ([email protected]_i), file:${SURELOG_DIR}/tests/TopParam/dut.sv, line:5:5, endln:8:7
+      |vpiOverriden:1
+      |vpiRhs:
+      \_ref_obj: ([email protected]_i.param), line:6:16, endln:6:21
+        |vpiParent:
+        \_param_assign: , line:13:15, endln:13:20
+        |vpiName:param
+        |vpiFullName:[email protected]_i.param
+        |vpiActual:
+        \_parameter: ([email protected]_i.param), line:13:15, endln:13:20
+      |vpiLhs:
+      \_parameter: ([email protected]_i.param), line:13:15, endln:13:20
+    |vpiDefName:work@test
+    |vpiDefFile:${SURELOG_DIR}/tests/TopParam/dut.sv
+    |vpiDefLineNo:12
+    |vpiInstance:
+    \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/TopParam/dut.sv, line:1:1, endln:10:10
+===================
+[  FATAL] : 0
+[ SYNTAX] : 0
+[  ERROR] : 1
+[WARNING] : 2
+[   NOTE] : 5
+
+============================== Begin RoundTrip Results ==============================
+[roundtrip]: ${SURELOG_DIR}/tests/TopParam/dut.sv | ${SURELOG_DIR}/build/regression/TopParam/roundtrip/dut_000.sv | 8 | 16 |
+============================== End RoundTrip Results ==============================
diff --git a/tests/TopParam/TopParam.sl b/tests/TopParam/TopParam.sl
@@ -0,0 +1 @@
+-parse -d uhdm -d coveruhdm -elabuhdm -d ast dut.sv -nobuiltin
diff --git a/tests/TopParam/dut.sv b/tests/TopParam/dut.sv
@@ -0,0 +1,16 @@
+module top #(
+    parameter param
+);
+
+    test #(
+        .param(param)
+    ) test_i (
+    );
+
+endmodule
+
+module test #(
+    parameter param
+)();
+
+endmodule
diff --git a/third_party/tests/CoresSweRVMP/CoresSweRVMP.log b/third_party/tests/CoresSweRVMP/CoresSweRVMP.log
@@ -82,15 +82,15 @@ CMake Deprecation Warning at CMakeLists.txt:1 (cmake_minimum_required):
 -- Build files have been written to: ${SURELOG_DIR}/build/regression/CoresSweRVMP/slpp_all/mp_preprocess
 [  6%] Generating 10_lsu_bus_intf.sv
 [ 12%] Generating 11_ifu_bp_ctl.sv
-[ 18%] Generating 15_exu.sv
-[ 25%] Generating 3_rvjtag_tap.sv
-[ 31%] Generating 16_dec_decode_ctl.sv
-[ 37%] Generating 13_ifu_mem_ctl.sv
-[ 43%] Generating 14_mem_lib.sv
+[ 18%] Generating 12_beh_lib.sv
+[ 25%] Generating 14_mem_lib.sv
+[ 31%] Generating 13_ifu_mem_ctl.sv
+[ 37%] Generating 15_exu.sv
+[ 43%] Generating 16_dec_decode_ctl.sv
 [ 50%] Generating 1_lsu_stbuf.sv
-[ 62%] Generating 4_dec_tlu_ctl.sv
-[ 62%] Generating 2_ahb_to_axi4.sv
-[ 68%] Generating 12_beh_lib.sv
+[ 56%] Generating 2_ahb_to_axi4.sv
+[ 62%] Generating 3_rvjtag_tap.sv
+[ 68%] Generating 4_dec_tlu_ctl.sv
 [ 75%] Generating 5_lsu_bus_buffer.sv
 [ 81%] Generating 6_dbg.sv
 [ 87%] Generating 7_axi4_to_ahb.sv

diff --git a/third_party/tests/YosysTests/YosysTests.log b/third_party/tests/YosysTests/YosysTests.log
@@ -8759,9 +8759,10 @@ Processing: -cd regression/issue_00790 testbench.v -writepp -parse -nocache -nob
 [WARNING] : 3
 [   NOTE] : 0
 Processing: -cd regression/issue_00603 top.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l top.v.log
+[ERR:EL0551] ${SURELOG_DIR}/third_party/tests/YosysTests/regression/issue_00603/top.v:4:15: Top-level parameter with no default value "K".
 [  FATAL] : 0
 [ SYNTAX] : 0
-[  ERROR] : 0
+[  ERROR] : 1
 [WARNING] : 0
 [   NOTE] : 0
 Processing: -cd regression/issue_00603 testbench.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l testbench.v.log
@@ -10965,6 +10966,6 @@ Processing: -cd regression/issue_01329 synchronizer.sv -writepp -parse -nocache
 Processed 1309 tests.
 [  FATAL] : 0
 [ SYNTAX] : 229
-[  ERROR] : 39
+[  ERROR] : 40
 [WARNING] : 2368
 [   NOTE] : 0