Skip to content

Commit

Permalink
Merge pull request #3983 from alainmarcel/alainmarcel-patch-1
Browse files Browse the repository at this point in the history 
32 bit size interface for values and 32 bit storage for string vals u…
  • Loading branch information
@alaindargelas
alaindargelas authored Sep 14, 2024
2 parents fbbe26e + 4ac89ef commit e023cda
Show file tree
Hide file tree
Showing 23 changed files with 1,740 additions and 509 deletions.
30 changes: 15 additions & 15 deletions include/Surelog/Expression/Value.h
View file
Original file line number Diff line number Diff line change
Expand Up @@ -59,8 +59,8 @@ class Value : public RTTI {

~Value() override {}

virtual int16_t getSize() const = 0; // size in bits
virtual int16_t getSize(
virtual int32_t getSize() const = 0; // size in bits
virtual int32_t getSize(
uint32_t wordIndex) const = 0; // size in bits of a multi-word value
// nb of 64 bits words necessary to encode the size
virtual uint16_t getNbWords() const = 0;
Expand Down Expand Up @@ -91,7 +91,7 @@ class Value : public RTTI {
virtual void set(uint64_t val) = 0;
virtual void set(int64_t val) = 0;
virtual void set(double val) = 0;
virtual void set(uint64_t val, Type type, int16_t size) = 0;
virtual void set(uint64_t val, Type type, int32_t size) = 0;
virtual void set(std::string_view val) = 0;
virtual void set(std::string_view val, Type type) = 0;
virtual bool operator<(const Value& rhs) const = 0;
Expand Down Expand Up @@ -166,7 +166,7 @@ class SValue final : public Value {
: m_type(Value::Type::Unsigned), m_size(0), m_valid(1), m_negative(0) {
m_value.u_int = 0;
}
SValue(int64_t val, int16_t size)
SValue(int64_t val, int32_t size)
: m_type(Value::Type::Integer),
m_size(size),
m_valid(1),
Expand Down Expand Up @@ -196,8 +196,8 @@ class SValue final : public Value {
}
~SValue() final;

int16_t getSize() const final { return m_size; }
int16_t getSize(uint32_t wordIndex) const final { return m_size; }
int32_t getSize() const final { return m_size; }
int32_t getSize(uint32_t wordIndex) const final { return m_size; }
void setRange(uint16_t lrange, uint16_t rrange) final {
m_lrange = lrange;
m_rrange = rrange;
Expand All @@ -219,7 +219,7 @@ class SValue final : public Value {
void set(uint64_t val) final;
void set(int64_t val) final;
void set(double val) final;
void set(uint64_t val, Type type, int16_t size) final;
void set(uint64_t val, Type type, int32_t size) final;

void set(std::string_view val) final {
m_type = Value::Type::None;
Expand Down Expand Up @@ -343,8 +343,8 @@ class LValue final : public Value {
LValue(int64_t val, Type type, int16_t size);
~LValue() final;

int16_t getSize() const final;
int16_t getSize(uint32_t wordIndex) const final {
int32_t getSize() const final;
int32_t getSize(uint32_t wordIndex) const final {
if (m_valueArray) {
return m_valueArray[wordIndex].m_size;
} else
Expand All @@ -371,7 +371,7 @@ class LValue final : public Value {
void set(uint64_t val) final;
void set(int64_t val) final;
void set(double val) final;
void set(uint64_t val, Type type, int16_t size) final;
void set(uint64_t val, Type type, int32_t size) final;
void set(std::string_view val) final {}
void set(std::string_view val, Type type) final {}
bool operator<(const Value& rhs) const final;
Expand Down Expand Up @@ -448,8 +448,8 @@ class StValue final : public Value {
: m_type(Type::String), m_value(val), m_size(val.size()), m_valid(true), m_typespec(nullptr) {}
~StValue() final;

int16_t getSize() const final { return m_size; }
int16_t getSize(uint32_t wordIndex) const final { return m_size; }
int32_t getSize() const final { return m_size; }
int32_t getSize(uint32_t wordIndex) const final { return m_size; }
void setRange(uint16_t lrange, uint16_t rrange) final {
m_lrange = lrange;
m_rrange = rrange;
Expand Down Expand Up @@ -489,7 +489,7 @@ class StValue final : public Value {
m_signed = true;
m_typespec = nullptr;
}
void set(uint64_t val, Type type, int16_t size) final {
void set(uint64_t val, Type type, int32_t size) final {
m_type = type;
m_value = std::to_string(val);
m_size = size;
Expand All @@ -508,7 +508,7 @@ class StValue final : public Value {
m_signed = false;
m_typespec = nullptr;
}
void set(std::string_view val, Type type, int16_t size) {
void set(std::string_view val, Type type, int32_t size) {
m_type = type;
m_value = val;
m_size = size;
Expand Down Expand Up @@ -606,7 +606,7 @@ class StValue final : public Value {
private:
Type m_type;
std::string m_value;
int16_t m_size = 0;
int32_t m_size = 0;
uint16_t m_valid = 0;
uint16_t m_lrange = 0;
uint16_t m_rrange = 0;
Expand Down
8 changes: 4 additions & 4 deletions src/Expression/Value.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -193,7 +193,7 @@ void SValue::set(double val) {
m_rrange = 0;
m_signed = true;
}
void SValue::set(uint64_t val, Type type, int16_t size) {
void SValue::set(uint64_t val, Type type, int32_t size) {
m_type = type;
m_value.u_int = val;
m_size = size;
Expand Down Expand Up @@ -858,8 +858,8 @@ void SValue::shiftRight(const Value* a, const Value* b) {
m_valid = a->isValid() && b->isValid();
}

int16_t LValue::getSize() const {
uint16_t size = 0;
int32_t LValue::getSize() const {
uint32_t size = 0;
for (int32_t i = 0; i < m_nbWords; i++) {
size += m_valueArray[i].m_size;
}
Expand Down Expand Up @@ -1118,7 +1118,7 @@ void LValue::set(double val) {
m_typespec = nullptr;
}

void LValue::set(uint64_t val, Type type, int16_t size) {
void LValue::set(uint64_t val, Type type, int32_t size) {
m_type = type;
m_nbWords = 1;
if (!m_valueArray) m_valueArray = new SValue[1];
Expand Down
32 changes: 16 additions & 16 deletions tests/DashYTest/DashYTest.log
View file
Original file line number Diff line number Diff line change
Expand Up @@ -43,6 +43,22 @@ n<> u<11> t<Top_level_rule> c<1> l<1:1> el<3:1>
AST_DEBUG_END
AST_DEBUG_BEGIN
LIB: work
FILE: ${SURELOG_DIR}/tests/DashYTest/lib/OR.v
n<> u<0> t<_INVALID_> f<0> l<0:0>
n<> u<1> t<Null_rule> p<11> s<10> l<1:1> el<1:0>
n<module> u<2> t<Module_keyword> p<6> s<3> l<1:1> el<1:7>
n<OR> u<3> t<StringConst> p<6> s<5> l<1:8> el<1:10>
n<> u<4> t<Port> p<5> l<1:11> el<1:11>
n<> u<5> t<List_of_ports> p<6> c<4> l<1:10> el<1:12>
n<> u<6> t<Module_nonansi_header> p<8> c<2> s<7> l<1:1> el<1:13>
n<> u<7> t<ENDMODULE> p<8> l<2:1> el<2:10>
n<> u<8> t<Module_declaration> p<9> c<6> l<1:1> el<2:10>
n<> u<9> t<Description> p<10> c<8> l<1:1> el<2:10>
n<> u<10> t<Source_text> p<11> c<9> l<1:1> el<2:10>
n<> u<11> t<Top_level_rule> c<1> l<1:1> el<3:1>
AST_DEBUG_END
AST_DEBUG_BEGIN
LIB: work
FILE: ${SURELOG_DIR}/tests/DashYTest/lib/SIM.v
n<> u<0> t<_INVALID_> f<0> l<0:0>
n<> u<1> t<Null_rule> p<29> s<28> l<1:1> el<1:0>
Expand Down Expand Up @@ -75,22 +91,6 @@ n<> u<27> t<Description> p<28> c<26> l<1:1> el<6:10>
n<> u<28> t<Source_text> p<29> c<27> l<1:1> el<6:10>
n<> u<29> t<Top_level_rule> c<1> l<1:1> el<7:1>
AST_DEBUG_END
AST_DEBUG_BEGIN
LIB: work
FILE: ${SURELOG_DIR}/tests/DashYTest/lib/OR.v
n<> u<0> t<_INVALID_> f<0> l<0:0>
n<> u<1> t<Null_rule> p<11> s<10> l<1:1> el<1:0>
n<module> u<2> t<Module_keyword> p<6> s<3> l<1:1> el<1:7>
n<OR> u<3> t<StringConst> p<6> s<5> l<1:8> el<1:10>
n<> u<4> t<Port> p<5> l<1:11> el<1:11>
n<> u<5> t<List_of_ports> p<6> c<4> l<1:10> el<1:12>
n<> u<6> t<Module_nonansi_header> p<8> c<2> s<7> l<1:1> el<1:13>
n<> u<7> t<ENDMODULE> p<8> l<2:1> el<2:10>
n<> u<8> t<Module_declaration> p<9> c<6> l<1:1> el<2:10>
n<> u<9> t<Description> p<10> c<8> l<1:1> el<2:10>
n<> u<10> t<Source_text> p<11> c<9> l<1:1> el<2:10>
n<> u<11> t<Top_level_rule> c<1> l<1:1> el<3:1>
AST_DEBUG_END
[INF:CP0300] Compilation...
[INF:CP0303] ${SURELOG_DIR}/tests/DashYTest/lib/AND.v:1:1: Compile module "work@AND".
[INF:CP0303] ${SURELOG_DIR}/tests/DashYTest/lib/OR.v:1:1: Compile module "work@OR".
Expand Down
8 changes: 6 additions & 2 deletions tests/HighLow/HighLow.log
View file
Original file line number Diff line number Diff line change
Expand Up @@ -298,7 +298,7 @@ AST_DEBUG_END
[INF:UH0706] Creating UHDM Model...
=== UHDM Object Stats Begin (Non-Elaborated Model) ===
begin 4
constant 41
constant 42
cont_assign 2
design 1
gen_if 4
Expand All @@ -320,7 +320,7 @@ sys_func_call 10
[INF:UH0707] Elaborating UHDM...
=== UHDM Object Stats Begin (Elaborated Model) ===
begin 4
constant 41
constant 42
cont_assign 3
design 1
gen_if 4
Expand Down Expand Up @@ -866,7 +866,10 @@ design: (work@top)
\_constant:
|vpiParent:
\_cont_assign: , line:12:10, endln:12:24
|vpiDecompile:2
|vpiSize:64
|UINT:2
|vpiConstType:9
|vpiLhs:
\_ref_obj: ([email protected]), line:12:10, endln:12:13
|vpiParent:
Expand Down Expand Up @@ -1061,6 +1064,7 @@ design: (work@top)
\_logic_typespec:
|vpiLeftRange:
\_constant:
|UINT:2
|vpiRightRange:
\_constant:
|UINT:1
Expand Down
1,225 changes: 1,225 additions & 0 deletions tests/LargeHexString/LargeHexString.log
View file

Large diffs are not rendered by default.

1 change: 1 addition & 0 deletions tests/LargeHexString/LargeHexString.sl
View file
Original file line number Diff line number Diff line change
@@ -0,0 +1 @@
-parse -d uhdm -d coveruhdm -elabuhdm -d ast dut.sv
13 changes: 13 additions & 0 deletions tests/LargeHexString/dut.sv
View file

Large diffs are not rendered by default.

14 changes: 7 additions & 7 deletions tests/LibraryIntercon/LibraryIntercon.log
View file
Original file line number Diff line number Diff line change
Expand Up @@ -6,31 +6,31 @@ LIB: work
${SURELOG_DIR}/tests/LibraryIntercon/lib.map

LIB: realLib
${SURELOG_DIR}/tests/LibraryIntercon/driver.svr
${SURELOG_DIR}/tests/LibraryIntercon/cmp.svr
${SURELOG_DIR}/tests/LibraryIntercon/driver.svr

LIB: logicLib
${SURELOG_DIR}/tests/LibraryIntercon/driver.sv
${SURELOG_DIR}/tests/LibraryIntercon/top.sv
${SURELOG_DIR}/tests/LibraryIntercon/cmp.sv
${SURELOG_DIR}/tests/LibraryIntercon/top.sv


[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/tests/LibraryIntercon/nets.pkg".
[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/tests/LibraryIntercon/lib.map".
[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/tests/LibraryIntercon/driver.svr".
[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/tests/LibraryIntercon/cmp.svr".
[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/tests/LibraryIntercon/driver.svr".
[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/tests/LibraryIntercon/driver.sv".
[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/tests/LibraryIntercon/top.sv".
[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/tests/LibraryIntercon/cmp.sv".
[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/tests/LibraryIntercon/top.sv".
[INF:PA0201] Parsing source file "${SURELOG_DIR}/tests/LibraryIntercon/nets.pkg".
[INF:PA0201] Parsing source file "${SURELOG_DIR}/tests/LibraryIntercon/driver.svr".
[INF:PA0201] Parsing source file "${SURELOG_DIR}/tests/LibraryIntercon/cmp.svr".
[INF:PA0201] Parsing source file "${SURELOG_DIR}/tests/LibraryIntercon/driver.svr".
[INF:PA0201] Parsing source file "${SURELOG_DIR}/tests/LibraryIntercon/driver.sv".
[INF:PA0201] Parsing source file "${SURELOG_DIR}/tests/LibraryIntercon/top.sv".
[INF:PA0201] Parsing source file "${SURELOG_DIR}/tests/LibraryIntercon/cmp.sv".
[INF:PA0201] Parsing source file "${SURELOG_DIR}/tests/LibraryIntercon/top.sv".
[WRN:PA0205] ${SURELOG_DIR}/tests/LibraryIntercon/nets.pkg:1:1: No timescale set for "NetsPkg".
[WRN:PA0205] ${SURELOG_DIR}/tests/LibraryIntercon/top.sv:1:1: No timescale set for "top".
[WRN:PA0205] ${SURELOG_DIR}/tests/LibraryIntercon/cmp.sv:2:1: No timescale set for "cmp".
[WRN:PA0205] ${SURELOG_DIR}/tests/LibraryIntercon/top.sv:1:1: No timescale set for "top".
[INF:CP0300] Compilation...
[INF:CP0301] ${SURELOG_DIR}/tests/LibraryIntercon/nets.pkg:1:1: Compile package "NetsPkg".
[INF:CP0303] ${SURELOG_DIR}/tests/LibraryIntercon/cmp.sv:2:1: Compile module "logicLib@cmp".
Expand Down
32 changes: 16 additions & 16 deletions tests/NonSynthUnusedMod/NonSynthUnusedMod.log
View file
Original file line number Diff line number Diff line change
Expand Up @@ -27,6 +27,22 @@ n<> u<21> t<Top_level_rule> c<1> l<1:1> el<8:1>
AST_DEBUG_END
AST_DEBUG_BEGIN
LIB: work
FILE: ${SURELOG_DIR}/tests/NonSynthUnusedMod/top.v
n<> u<0> t<_INVALID_> f<0> l<0:0>
n<> u<1> t<Null_rule> p<11> s<10> l<1:1> el<1:0>
n<module> u<2> t<Module_keyword> p<6> s<3> l<1:1> el<1:7>
n<top> u<3> t<StringConst> p<6> s<5> l<1:8> el<1:11>
n<> u<4> t<Port> p<5> l<1:12> el<1:12>
n<> u<5> t<List_of_ports> p<6> c<4> l<1:11> el<1:13>
n<> u<6> t<Module_nonansi_header> p<8> c<2> s<7> l<1:1> el<1:14>
n<> u<7> t<ENDMODULE> p<8> l<3:1> el<3:10>
n<> u<8> t<Module_declaration> p<9> c<6> l<1:1> el<3:10>
n<> u<9> t<Description> p<10> c<8> l<1:1> el<3:10>
n<> u<10> t<Source_text> p<11> c<9> l<1:1> el<3:10>
n<> u<11> t<Top_level_rule> c<1> l<1:1> el<4:1>
AST_DEBUG_END
AST_DEBUG_BEGIN
LIB: work
FILE: ${SURELOG_DIR}/tests/NonSynthUnusedMod/nonsynth.v
n<> u<0> t<_INVALID_> f<0> l<0:0>
n<> u<1> t<Null_rule> p<38> s<37> l<1:1> el<1:0>
Expand Down Expand Up @@ -68,22 +84,6 @@ n<> u<36> t<Description> p<37> c<35> l<1:1> el<7:10>
n<> u<37> t<Source_text> p<38> c<36> l<1:1> el<7:10>
n<> u<38> t<Top_level_rule> c<1> l<1:1> el<8:1>
AST_DEBUG_END
AST_DEBUG_BEGIN
LIB: work
FILE: ${SURELOG_DIR}/tests/NonSynthUnusedMod/top.v
n<> u<0> t<_INVALID_> f<0> l<0:0>
n<> u<1> t<Null_rule> p<11> s<10> l<1:1> el<1:0>
n<module> u<2> t<Module_keyword> p<6> s<3> l<1:1> el<1:7>
n<top> u<3> t<StringConst> p<6> s<5> l<1:8> el<1:11>
n<> u<4> t<Port> p<5> l<1:12> el<1:12>
n<> u<5> t<List_of_ports> p<6> c<4> l<1:11> el<1:13>
n<> u<6> t<Module_nonansi_header> p<8> c<2> s<7> l<1:1> el<1:14>
n<> u<7> t<ENDMODULE> p<8> l<3:1> el<3:10>
n<> u<8> t<Module_declaration> p<9> c<6> l<1:1> el<3:10>
n<> u<9> t<Description> p<10> c<8> l<1:1> el<3:10>
n<> u<10> t<Source_text> p<11> c<9> l<1:1> el<3:10>
n<> u<11> t<Top_level_rule> c<1> l<1:1> el<4:1>
AST_DEBUG_END
[INF:CP0300] Compilation...
[INF:CP0303] ${SURELOG_DIR}/tests/NonSynthUnusedMod/dut.sv:1:1: Compile module "work@dut".
[INF:CP0303] ${SURELOG_DIR}/tests/NonSynthUnusedMod/nonsynth.v:1:1: Compile module "work@nonsynth".
Expand Down
6 changes: 3 additions & 3 deletions tests/OldLibrary/OldLibrary.log
View file
Original file line number Diff line number Diff line change
@@ -1,16 +1,16 @@
[INF:CM0023] Creating log file "${SURELOG_DIR}/build/regression/OldLibrary/slpp_all/surelog.log".
[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/tests/OldLibrary/top.v".
[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/tests/OldLibrary/lib/CELL3.v".
[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/tests/OldLibrary/lib/CELL2.v".
[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/tests/OldLibrary/lib/CELL1.v".
[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/tests/OldLibrary/lib/CELL3.v".
[INF:PA0201] Parsing source file "${SURELOG_DIR}/tests/OldLibrary/top.v".
[INF:PA0201] Parsing source file "${SURELOG_DIR}/tests/OldLibrary/lib/CELL3.v".
[INF:PA0201] Parsing source file "${SURELOG_DIR}/tests/OldLibrary/lib/CELL2.v".
[INF:PA0201] Parsing source file "${SURELOG_DIR}/tests/OldLibrary/lib/CELL1.v".
[INF:PA0201] Parsing source file "${SURELOG_DIR}/tests/OldLibrary/lib/CELL3.v".
[WRN:PA0205] ${SURELOG_DIR}/tests/OldLibrary/top.v:1:1: No timescale set for "top".
[WRN:PA0205] ${SURELOG_DIR}/tests/OldLibrary/lib/CELL3.v:1:1: No timescale set for "CELL3".
[WRN:PA0205] ${SURELOG_DIR}/tests/OldLibrary/lib/CELL2.v:1:1: No timescale set for "CELL2".
[WRN:PA0205] ${SURELOG_DIR}/tests/OldLibrary/lib/CELL1.v:1:1: No timescale set for "CELL1".
[WRN:PA0205] ${SURELOG_DIR}/tests/OldLibrary/lib/CELL3.v:1:1: No timescale set for "CELL3".
[INF:CP0300] Compilation...
[INF:CP0303] ${SURELOG_DIR}/tests/OldLibrary/lib/CELL1.v:1:1: Compile module "work@CELL1".
[INF:CP0305] ${SURELOG_DIR}/tests/OldLibrary/lib/CELL2.v:1:1: Compile udp "work@CELL2".
Expand Down
60 changes: 30 additions & 30 deletions tests/PreprocLine/PreprocLine.log
View file
Original file line number Diff line number Diff line change
Expand Up @@ -13,38 +13,38 @@ n<top> u<3> t<StringConst> p<4> l<1:8> el<1:11>
n<> u<4> t<Module_ansi_header> p<66> c<2> s<64> l<1:1> el<1:12>
n<> u<5> t<Dollar_keyword> p<17> s<6> l<3:9> el<3:10>
n<display> u<6> t<StringConst> p<17> s<16> l<3:10> el<3:17>
n<"${SURELOG_DIR}/tests/PreprocLine/dut.sv"> u<7> t<StringLiteral> p<8> l<3:18> el<3:98>
n<> u<8> t<Primary_literal> p<9> c<7> l<3:18> el<3:98>
n<> u<9> t<Primary> p<10> c<8> l<3:18> el<3:98>
n<> u<10> t<Expression> p<16> c<9> s<15> l<3:18> el<3:98>
n<3> u<11> t<IntConst> p<12> l<3:100> el<3:101>
n<> u<12> t<Primary_literal> p<13> c<11> l<3:100> el<3:101>
n<> u<13> t<Primary> p<14> c<12> l<3:100> el<3:101>
n<> u<14> t<Expression> p<15> c<13> l<3:100> el<3:101>
n<> u<15> t<Argument> p<16> c<14> l<3:100> el<3:101>
n<> u<16> t<List_of_arguments> p<17> c<10> l<3:18> el<3:101>
n<> u<17> t<Subroutine_call> p<18> c<5> l<3:9> el<3:102>
n<> u<18> t<Subroutine_call_statement> p<19> c<17> l<3:9> el<3:103>
n<> u<19> t<Statement_item> p<20> c<18> l<3:9> el<3:103>
n<> u<20> t<Statement> p<21> c<19> l<3:9> el<3:103>
n<> u<21> t<Statement_or_null> p<57> c<20> s<38> l<3:9> el<3:103>
n<"${SURELOG_DIR}/tests/PreprocLine/dut.sv"> u<7> t<StringLiteral> p<8> l<3:18> el<3:64>
n<> u<8> t<Primary_literal> p<9> c<7> l<3:18> el<3:64>
n<> u<9> t<Primary> p<10> c<8> l<3:18> el<3:64>
n<> u<10> t<Expression> p<16> c<9> s<15> l<3:18> el<3:64>
n<3> u<11> t<IntConst> p<12> l<3:66> el<3:67>
n<> u<12> t<Primary_literal> p<13> c<11> l<3:66> el<3:67>
n<> u<13> t<Primary> p<14> c<12> l<3:66> el<3:67>
n<> u<14> t<Expression> p<15> c<13> l<3:66> el<3:67>
n<> u<15> t<Argument> p<16> c<14> l<3:66> el<3:67>
n<> u<16> t<List_of_arguments> p<17> c<10> l<3:18> el<3:67>
n<> u<17> t<Subroutine_call> p<18> c<5> l<3:9> el<3:68>
n<> u<18> t<Subroutine_call_statement> p<19> c<17> l<3:9> el<3:69>
n<> u<19> t<Statement_item> p<20> c<18> l<3:9> el<3:69>
n<> u<20> t<Statement> p<21> c<19> l<3:9> el<3:69>
n<> u<21> t<Statement_or_null> p<57> c<20> s<38> l<3:9> el<3:69>
n<> u<22> t<Dollar_keyword> p<34> s<23> l<5:9> el<5:10>
n<display> u<23> t<StringConst> p<34> s<33> l<5:10> el<5:17>
n<"${SURELOG_DIR}/tests/PreprocLine/fake.v"> u<24> t<StringLiteral> p<25> l<5:18> el<5:98>
n<> u<25> t<Primary_literal> p<26> c<24> l<5:18> el<5:98>
n<> u<26> t<Primary> p<27> c<25> l<5:18> el<5:98>
n<> u<27> t<Expression> p<33> c<26> s<32> l<5:18> el<5:98>
n<102> u<28> t<IntConst> p<29> l<5:100> el<5:103>
n<> u<29> t<Primary_literal> p<30> c<28> l<5:100> el<5:103>
n<> u<30> t<Primary> p<31> c<29> l<5:100> el<5:103>
n<> u<31> t<Expression> p<32> c<30> l<5:100> el<5:103>
n<> u<32> t<Argument> p<33> c<31> l<5:100> el<5:103>
n<> u<33> t<List_of_arguments> p<34> c<27> l<5:18> el<5:103>
n<> u<34> t<Subroutine_call> p<35> c<22> l<5:9> el<5:104>
n<> u<35> t<Subroutine_call_statement> p<36> c<34> l<5:9> el<5:105>
n<> u<36> t<Statement_item> p<37> c<35> l<5:9> el<5:105>
n<> u<37> t<Statement> p<38> c<36> l<5:9> el<5:105>
n<> u<38> t<Statement_or_null> p<57> c<37> s<55> l<5:9> el<5:105>
n<"${SURELOG_DIR}/tests/PreprocLine/fake.v"> u<24> t<StringLiteral> p<25> l<5:18> el<5:64>
n<> u<25> t<Primary_literal> p<26> c<24> l<5:18> el<5:64>
n<> u<26> t<Primary> p<27> c<25> l<5:18> el<5:64>
n<> u<27> t<Expression> p<33> c<26> s<32> l<5:18> el<5:64>
n<102> u<28> t<IntConst> p<29> l<5:66> el<5:69>
n<> u<29> t<Primary_literal> p<30> c<28> l<5:66> el<5:69>
n<> u<30> t<Primary> p<31> c<29> l<5:66> el<5:69>
n<> u<31> t<Expression> p<32> c<30> l<5:66> el<5:69>
n<> u<32> t<Argument> p<33> c<31> l<5:66> el<5:69>
n<> u<33> t<List_of_arguments> p<34> c<27> l<5:18> el<5:69>
n<> u<34> t<Subroutine_call> p<35> c<22> l<5:9> el<5:70>
n<> u<35> t<Subroutine_call_statement> p<36> c<34> l<5:9> el<5:71>
n<> u<36> t<Statement_item> p<37> c<35> l<5:9> el<5:71>
n<> u<37> t<Statement> p<38> c<36> l<5:9> el<5:71>
n<> u<38> t<Statement_or_null> p<57> c<37> s<55> l<5:9> el<5:71>
n<> u<39> t<Dollar_keyword> p<51> s<40> f<0> l<10:9> el<10:10>
n<display> u<40> t<StringConst> p<51> s<50> f<0> l<10:10> el<10:17>
n<""> u<41> t<StringLiteral> p<42> f<0> l<10:18> el<10:20>
Expand Down
Loading

0 comments on commit e023cda

Please sign in to comment.