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interface binding
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@alaindargelas
alaindargelas committed Apr 23, 2023
1 parent 1dcac51 commit ec4f3c4
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Showing 23 changed files with 101 additions and 170 deletions.
19 changes: 19 additions & 0 deletions .vscode/launch.json
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Original file line number Diff line number Diff line change
Expand Up @@ -1857,6 +1857,25 @@
"ignoreFailures": true
}
]
},
{
"name": "YosysVerx",
"type": "cppdbg",
"request": "launch",
"program": "${workspaceFolder}/dbuild/bin/surelog",
"args": ["-f", "YosysVerx.sl"],
"stopAtEntry": false,
"cwd": "${workspaceFolder}/third_party/tests/YosysVerx",
"environment": [],
"externalConsole": false,
"MIMode": "gdb",
"setupCommands": [
{
"description": "Enable pretty-printing for gdb",
"text": "-enable-pretty-printing",
"ignoreFailures": true
}
]
}
]
}
50 changes: 30 additions & 20 deletions src/DesignCompile/UhdmWriter.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -1932,11 +1932,6 @@ bool UhdmWriter::writeElabGenScope(Serializer& s, ModuleInstance* instance,
}
}

if (mod) {
lateTypedefBinding(s, mod, m, componentMap);
lateBinding(s, mod, m, componentMap);
}

return true;
}

Expand Down Expand Up @@ -2893,7 +2888,27 @@ void UhdmWriter::lateBinding(UHDM::Serializer& s, DesignComponent* mod,
parent = parent->VpiParent();
}
if (ref->Actual_group()) continue;

if (m->UhdmType() == uhdmmodule_inst) {
module_inst* minst = (module_inst*)m;
if (minst->Interfaces()) {
for (auto n : *minst->Interfaces()) {
if (n->VpiName() == name) {
ref->Actual_group(n);
break;
}
}
if (ref->Actual_group()) continue;
}
if (minst->Interface_arrays()) {
for (auto n : *minst->Interface_arrays()) {
if (n->VpiName() == name) {
ref->Actual_group(n);
break;
}
}
if (ref->Actual_group()) continue;
}
}
if (m->UhdmType() == uhdmmodule_inst ||
m->UhdmType() == uhdminterface_inst || m->UhdmType() == uhdmprogram) {
instance* inst = (instance*)m;
Expand Down Expand Up @@ -3200,13 +3215,6 @@ bool UhdmWriter::writeElabModule(Serializer& s, ModuleInstance* instance,
}
}
}

if (mod) {
lateTypedefBinding(s, mod, m, componentMap);
lateBinding(s, mod, m, componentMap);
lateTypedefBinding(s, mod, m, componentMap);
}

return true;
}

Expand Down Expand Up @@ -3379,12 +3387,6 @@ bool UhdmWriter::writeElabInterface(Serializer& s, ModuleInstance* instance,
}
}
}

if (mod) {
lateTypedefBinding(s, mod, m, componentMap);
lateBinding(s, mod, m, componentMap);
}

return true;
}

Expand Down Expand Up @@ -3452,7 +3454,6 @@ void UhdmWriter::writeInstance(ModuleDefinition* mod, ModuleInstance* instance,
VectorOfprimitive* subPrimitives = nullptr;
VectorOfprimitive_array* subPrimitiveArrays = nullptr;
VectorOfgen_scope_array* subGenScopeArrays = nullptr;

if (m->UhdmType() == uhdmmodule_inst) {
writeElabModule(s, instance, (module_inst*)m, exprBuilder);
} else if (m->UhdmType() == uhdmgen_scope) {
Expand Down Expand Up @@ -3796,6 +3797,15 @@ void UhdmWriter::writeInstance(ModuleDefinition* mod, ModuleInstance* instance,
}
}
}

if (mod && netlist) {
scope* sc = dynamic_cast<scope*>(m);
if (sc) {
lateTypedefBinding(s, mod, sc, componentMap);
lateBinding(s, mod, sc, componentMap);
lateTypedefBinding(s, mod, sc, componentMap);
}
}
}

vpiHandle UhdmWriter::write(PathId uhdmFileId) {
Expand Down
10 changes: 3 additions & 7 deletions tests/InterfType/InterfType.log
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Original file line number Diff line number Diff line change
Expand Up @@ -120,7 +120,7 @@ design 1
int_typespec 2
interface_inst 7
interface_typespec 2
logic_net 2
logic_net 1
module_inst 6
param_assign 2
parameter 2
Expand All @@ -136,7 +136,7 @@ design 1
int_typespec 2
interface_inst 7
interface_typespec 2
logic_net 2
logic_net 1
module_inst 6
param_assign 2
parameter 2
Expand Down Expand Up @@ -239,16 +239,12 @@ design: (work@dut)
\_ref_obj: (i_types), line:16:20, endln:16:27
|vpiName:i_types
|vpiActual:
\_logic_net: (i_types)
\_interface_inst: work@tnoc_types (work@dut.i_types), file:${SURELOG_DIR}/tests/InterfType/dut.sv, line:15:1, endln:15:26
|uhdmtopModules:
\_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/InterfType/dut.sv, line:13:1, endln:18:10
|vpiName:work@dut
|vpiDefName:work@dut
|vpiTop:1
|vpiNet:
\_logic_net: (i_types)
|vpiName:i_types
|vpiNetType:1
|vpiTopModule:1
|vpiInterface:
\_interface_inst: work@tnoc_types ([email protected]_types), file:${SURELOG_DIR}/tests/InterfType/dut.sv, line:15:1, endln:15:26
Expand Down
12 changes: 4 additions & 8 deletions tests/InterfaceElab/InterfaceElab.log
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Original file line number Diff line number Diff line change
Expand Up @@ -196,7 +196,7 @@ int_typespec 2
interface_inst 4
interface_typespec 6
io_decl 4
logic_net 7
logic_net 6
logic_typespec 6
logic_var 2
modport 4
Expand All @@ -218,7 +218,7 @@ int_typespec 2
interface_inst 4
interface_typespec 6
io_decl 4
logic_net 7
logic_net 6
logic_typespec 6
logic_var 2
modport 4
Expand Down Expand Up @@ -373,7 +373,7 @@ design: (work@testharness)
\_ref_obj: (reg_bus), line:27:34, endln:27:41
|vpiName:reg_bus
|vpiActual:
\_logic_net: (reg_bus)
\_interface_inst: work@REG_BUS ([email protected]_peripherals.reg_bus), file:${SURELOG_DIR}/tests/InterfaceElab/dut.sv, line:23:4, endln:25:23
|uhdmallModules:
\_module_inst: work@testharness (work@testharness), file:${SURELOG_DIR}/tests/InterfaceElab/dut.sv, line:32:1, endln:36:10
|vpiParent:
Expand Down Expand Up @@ -410,10 +410,6 @@ design: (work@testharness)
|vpiName:clk_i
|vpiFullName:[email protected]_peripherals.clk_i
|vpiNetType:1
|vpiNet:
\_logic_net: (reg_bus)
|vpiName:reg_bus
|vpiNetType:1
|vpiInstance:
\_module_inst: work@testharness (work@testharness), file:${SURELOG_DIR}/tests/InterfaceElab/dut.sv, line:32:1, endln:36:10
|vpiInterface:
Expand Down Expand Up @@ -565,7 +561,7 @@ design: (work@testharness)
|vpiName:reg_bus
|vpiFullName:[email protected]_peripherals.reg_bus
|vpiActual:
\_logic_net: (reg_bus)
\_interface_inst: work@REG_BUS ([email protected]_peripherals.reg_bus), file:${SURELOG_DIR}/tests/InterfaceElab/dut.sv, line:23:4, endln:25:23
|vpiLowConn:
\_ref_obj: ([email protected]_peripherals.i_apb_to_reg.reg_o), line:27:27, endln:27:32
|vpiParent:
Expand Down
12 changes: 4 additions & 8 deletions tests/InterfaceModPort/InterfaceModPort.log
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Original file line number Diff line number Diff line change
Expand Up @@ -1215,7 +1215,7 @@ int_var 4
interface_inst 7
interface_typespec 14
io_decl 116
logic_net 27
logic_net 26
logic_typespec 54
logic_var 47
modport 13
Expand Down Expand Up @@ -2136,7 +2136,7 @@ design: (work@interface_modports)
\_ref_obj: (miff), line:120:20, endln:120:24
|vpiName:miff
|vpiActual:
\_logic_net: (miff)
\_interface_inst: work@mem_if (work@interface_modports.miff), file:${SURELOG_DIR}/tests/InterfaceModPort/top.v, line:119:1, endln:119:18
|vpiRefModule:
\_ref_module: work@memory_model (U_model), line:121:14, endln:121:21
|vpiParent:
Expand All @@ -2151,7 +2151,7 @@ design: (work@interface_modports)
\_ref_obj: (miff), line:121:22, endln:121:26
|vpiName:miff
|vpiActual:
\_logic_net: (miff)
\_interface_inst: work@mem_if (work@interface_modports.miff), file:${SURELOG_DIR}/tests/InterfaceModPort/top.v, line:119:1, endln:119:18
|vpiRefModule:
\_ref_module: work@test (U_test), line:122:8, endln:122:14
|vpiParent:
Expand All @@ -2166,7 +2166,7 @@ design: (work@interface_modports)
\_ref_obj: (miff), line:122:15, endln:122:19
|vpiName:miff
|vpiActual:
\_logic_net: (miff)
\_interface_inst: work@mem_if (work@interface_modports.miff), file:${SURELOG_DIR}/tests/InterfaceModPort/top.v, line:119:1, endln:119:18
|uhdmallModules:
\_module_inst: work@memory_ctrl (work@memory_ctrl), file:${SURELOG_DIR}/tests/InterfaceModPort/top.v, line:87:1, endln:94:10
|vpiParent:
Expand Down Expand Up @@ -2544,10 +2544,6 @@ design: (work@interface_modports)
\_interface_typespec: (mem_if), line:99:14, endln:99:20
|vpiName:tb
|vpiIsModPort:1
|vpiNet:
\_logic_net: (miff)
|vpiName:miff
|vpiNetType:1
|vpiTopModule:1
|vpiInterface:
\_interface_inst: work@mem_if (work@interface_modports.miff), file:${SURELOG_DIR}/tests/InterfaceModPort/top.v, line:119:1, endln:119:18
Expand Down
12 changes: 4 additions & 8 deletions tests/ModPortParam/ModPortParam.log
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Original file line number Diff line number Diff line change
Expand Up @@ -107,7 +107,7 @@ design 1
interface_inst 4
interface_typespec 6
io_decl 4
logic_net 2
logic_net 1
modport 4
module_inst 5
port 3
Expand All @@ -121,7 +121,7 @@ design 1
interface_inst 4
interface_typespec 6
io_decl 4
logic_net 2
logic_net 1
modport 4
module_inst 5
port 4
Expand Down Expand Up @@ -211,16 +211,12 @@ design: (work@Core)
\_ref_obj: (perfCounterIF), line:16:19, endln:16:32
|vpiName:perfCounterIF
|vpiActual:
\_logic_net: (perfCounterIF)
\_interface_inst: work@PerformanceCounterIF (work@Core.perfCounterIF), file:${SURELOG_DIR}/tests/ModPortParam/dut.sv, line:14:2, endln:14:40
|uhdmtopModules:
\_module_inst: work@Core (work@Core), file:${SURELOG_DIR}/tests/ModPortParam/dut.sv, line:13:1, endln:17:10
|vpiName:work@Core
|vpiDefName:work@Core
|vpiTop:1
|vpiNet:
\_logic_net: (perfCounterIF)
|vpiName:perfCounterIF
|vpiNetType:1
|vpiTopModule:1
|vpiInterface:
\_interface_inst: work@PerformanceCounterIF ([email protected]), file:${SURELOG_DIR}/tests/ModPortParam/dut.sv, line:14:2, endln:14:40
Expand Down Expand Up @@ -270,7 +266,7 @@ design: (work@Core)
|vpiName:perfCounterIF
|vpiFullName:[email protected]
|vpiActual:
\_logic_net: (perfCounterIF)
\_interface_inst: work@PerformanceCounterIF (work@Core.perfCounterIF), file:${SURELOG_DIR}/tests/ModPortParam/dut.sv, line:14:2, endln:14:40
|vpiLowConn:
\_ref_obj: ([email protected]), line:16:19, endln:16:32
|vpiParent:
Expand Down
14 changes: 3 additions & 11 deletions tests/OneNetInterf/OneNetInterf.log
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Original file line number Diff line number Diff line change
Expand Up @@ -60,7 +60,7 @@ immediate_assert 2
initial 1
interface_inst 7
interface_typespec 5
logic_net 31
logic_net 29
logic_typespec 37
module_inst 18
operation 2
Expand Down Expand Up @@ -555,7 +555,7 @@ design: (work@dut)
\_ref_obj: (conntb), line:4:18, endln:4:24
|vpiName:conntb
|vpiActual:
\_logic_net: (conntb)
\_interface_inst: work@ConnectTB (work@dut.conntb), file:${SURELOG_DIR}/tests/OneNetInterf/dut.v, line:3:3, endln:3:41
|uhdmallModules:
\_module_inst: work@middle (work@middle), file:${SURELOG_DIR}/tests/OneNetInterf/dut.v, line:10:1, endln:12:10
|vpiParent:
Expand Down Expand Up @@ -675,7 +675,7 @@ design: (work@dut)
\_ref_obj: (conntb), line:17:15, endln:17:21
|vpiName:conntb
|vpiActual:
\_logic_net: (conntb)
\_interface_inst: work@ConnectTB (work@tb.conntb), file:${SURELOG_DIR}/tests/OneNetInterf/tb.v, line:16:3, endln:16:41
|vpiRefModule:
\_ref_module: work@TESTBENCH (tb), line:18:13, endln:18:15
|vpiParent:
Expand Down Expand Up @@ -735,10 +735,6 @@ design: (work@dut)
|vpiName:o
|vpiFullName:[email protected]
|vpiNetType:48
|vpiNet:
\_logic_net: (conntb)
|vpiName:conntb
|vpiNetType:1
|vpiTopModule:1
|vpiPort:
\_port: (i), line:2:24, endln:2:25
Expand Down Expand Up @@ -1070,10 +1066,6 @@ design: (work@dut)
|vpiName:o
|vpiFullName:[email protected]
|vpiNetType:1
|vpiNet:
\_logic_net: (conntb)
|vpiName:conntb
|vpiNetType:1
|vpiTopModule:1
|vpiInterface:
\_interface_inst: work@ConnectTB ([email protected]), file:${SURELOG_DIR}/tests/OneNetInterf/tb.v, line:16:3, endln:16:41
Expand Down
14 changes: 3 additions & 11 deletions tests/OneNetModPort/OneNetModPort.log
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Original file line number Diff line number Diff line change
Expand Up @@ -57,7 +57,7 @@ initial 1
interface_inst 7
interface_typespec 8
io_decl 24
logic_net 13
logic_net 11
logic_typespec 20
logic_var 8
modport 12
Expand Down Expand Up @@ -520,7 +520,7 @@ design: (work@TOP)
\_ref_obj: (conntb), line:18:16, endln:18:22
|vpiName:conntb
|vpiActual:
\_logic_net: (conntb)
\_interface_inst: work@ConnectTB (work@TOP.conntb), file:${SURELOG_DIR}/tests/OneNetModPort/tb.v, line:16:3, endln:16:22
|uhdmallModules:
\_module_inst: work@dut (work@dut), file:${SURELOG_DIR}/tests/OneNetModPort/dut.v, line:2:1, endln:7:10
|vpiParent:
Expand Down Expand Up @@ -637,7 +637,7 @@ design: (work@TOP)
\_ref_obj: (conntb), line:6:18, endln:6:24
|vpiName:conntb
|vpiActual:
\_logic_net: (conntb)
\_interface_inst: work@ConnectTB ([email protected].conntb), file:${SURELOG_DIR}/tests/OneNetModPort/dut.v, line:5:3, endln:5:22
|uhdmallModules:
\_module_inst: work@middle (work@middle), file:${SURELOG_DIR}/tests/OneNetModPort/dut.v, line:22:1, endln:24:10
|vpiParent:
Expand Down Expand Up @@ -743,10 +743,6 @@ design: (work@TOP)
\_interface_typespec: (ConnectTB), line:1:21, endln:1:30
|vpiName:tb
|vpiIsModPort:1
|vpiNet:
\_logic_net: (conntb)
|vpiName:conntb
|vpiNetType:1
|vpiTopModule:1
|vpiInterface:
\_interface_inst: work@ConnectTB ([email protected]), file:${SURELOG_DIR}/tests/OneNetModPort/tb.v, line:16:3, endln:16:22
Expand Down Expand Up @@ -842,10 +838,6 @@ design: (work@TOP)
|vpiName:o
|vpiFullName:[email protected]
|vpiNetType:48
|vpiNet:
\_logic_net: (conntb)
|vpiName:conntb
|vpiNetType:1
|vpiInstance:
\_module_inst: work@TOP (work@TOP), file:${SURELOG_DIR}/tests/OneNetModPort/tb.v, line:15:1, endln:19:10
|vpiPort:
Expand Down

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