Unbound for loop support

src/DesignCompile/UhdmWriter.cpp

@@ -3163,7 +3163,17 @@ void UhdmWriter::lateBinding(Serializer& s, DesignComponent* mod, scope* m) {
 
     const any* parent = ref->VpiParent();
     while (parent) {
-      if (parent->UhdmType() == uhdmfunction) {
+      if (parent->UhdmType() == uhdmdesign) {
+        design* d = (design*) parent;
+        if (auto params = d->Parameters()) {
+          for (auto decl : *params) {
+            if (decl->VpiName() == name) {
+              ref->Actual_group(decl);
+              break;
+            }
+          }
+        }
+      } else if (parent->UhdmType() == uhdmfunction) {
         function* func = (function*)parent;
         if (parent->VpiName() == name) {
           if (const any* ret = func->Return()) {

tests/ConstCapital/ConstCapital.log

@@ -208,7 +208,7 @@ design: (work@test)
         |vpiName:foo
         |vpiFullName:[email protected]
         |vpiActual:
-        \_logic_net: (work@test.foo), line:10:5, endln:10:8
+        \_parameter: (foo), line:1:15, endln:1:18
       |vpiOperand:
       \_constant: , line:10:12, endln:10:20
         |vpiParent:
@@ -244,7 +244,7 @@ design: (work@test)
         |vpiName:foo2
         |vpiFullName:[email protected]
         |vpiActual:
-        \_logic_net: (work@test.foo2), line:15:5, endln:15:9
+        \_parameter: (foo2), line:2:15, endln:2:19
       |vpiOperand:
       \_constant: , line:15:13, endln:15:18
         |vpiParent:

tests/UnboundForLoop/UnboundForLoop.sl

@@ -0,0 +1 @@
+-parse -d uhdm -synth -d coveruhdm -elabuhdm -d ast dut.sv -nobuiltin

tests/UnboundForLoop/dut.sv

@@ -0,0 +1,9 @@
+module signed_shifter (
+  input wire [1:0] i,
+  output reg signed [3:0] Q );
+  integer j;
+  always @ * begin
+    for(j=0;j<i;j=j+1) Q = 1'b1;
+  end
+endmodule
+

third_party/tests/CoresSweRVMP/CoresSweRVMP.log

@@ -65,11 +65,11 @@ Running: cd ${SURELOG_DIR}/build/regression/CoresSweRVMP/slpp_all/mp_preprocess;
 -- Generating done
 -- Build files have been written to: ${SURELOG_DIR}/build/regression/CoresSweRVMP/slpp_all/mp_preprocess
 [  6%] Generating 10_lsu_bus_intf.sv
-[ 12%] Generating 12_beh_lib.sv
-[ 18%] Generating 11_ifu_bp_ctl.sv
+[ 12%] Generating 11_ifu_bp_ctl.sv
+[ 18%] Generating 12_beh_lib.sv
 [ 25%] Generating 13_ifu_mem_ctl.sv
-[ 31%] Generating 15_exu.sv
-[ 37%] Generating 14_mem_lib.sv
+[ 31%] Generating 14_mem_lib.sv
+[ 37%] Generating 15_exu.sv
 [ 43%] Generating 16_dec_decode_ctl.sv
 [ 50%] Generating 1_lsu_stbuf.sv
 [ 56%] Generating 2_ahb_to_axi4.sv

third_party/tests/Scr1/Scr1.log

@@ -259,7 +259,7 @@ int_var                                               40
 integer_typespec                                      59
 integer_var                                            3
 io_decl                                               27
-logic_net                                           2985
+logic_net                                           2757
 logic_typespec                                      4195
 logic_var                                            828
 method_func_call                                       5

third_party/tests/Scr1SvTests/Scr1SvTests.log

@@ -191,7 +191,7 @@ int_var                                               32
 integer_typespec                                      74
 integer_var                                            3
 io_decl                                               27
-logic_net                                           3237
+logic_net                                           3006
 logic_typespec                                      4682
 logic_var                                           1058
 method_func_call                                       4