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Multiple generate blocks #3957

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Jan 14, 2024
Merged

Multiple generate blocks #3957

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49 changes: 39 additions & 10 deletions src/DesignCompile/DesignElaboration.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -851,7 +851,6 @@ void DesignElaboration::elaborateInstance_(

std::vector<NodeId> subInstances =
fC->sl_collect_all(nodeId, types, stopPoints);
bool elaborated = false;
for (auto subInstanceId : subInstances) {
VObjectType type = fC->Type(subInstanceId);
std::vector<NodeId> subSubInstances;
Expand Down Expand Up @@ -894,10 +893,45 @@ void DesignElaboration::elaborateInstance_(
} else {
subSubInstances.push_back(subInstanceId);
}
elaborated = true;
NetlistElaboration* nelab = new NetlistElaboration(m_compileDesign);
nelab->elaborateInstance(parent);
delete nelab;
}

NetlistElaboration* nelab = new NetlistElaboration(m_compileDesign);
nelab->elaborateInstance(parent);
delete nelab;

for (auto subInstanceId : subInstances) {
VObjectType type = fC->Type(subInstanceId);
std::vector<NodeId> subSubInstances;
std::string instName;
if (type == VObjectType::paGenerate_region) {
NodeId Generate_item = fC->Child(subInstanceId);
if (fC->Type(Generate_item) != VObjectType::paGenerate_item) {
continue;
}
NodeId nameId = fC->Child(Generate_item);
if (fC->Name(nameId)) {
instName = fC->SymName(nameId);
subSubInstances.push_back(subInstanceId);
} else {
while (Generate_item) {
std::vector<NodeId> subIds =
fC->sl_collect_all(Generate_item, types, stopPoints);
if (!subIds.empty()) {
for (auto id : subIds) {
subSubInstances.push_back(id);
}
} else {
}
Generate_item = fC->Sibling(Generate_item);
if (Generate_item &&
(fC->Type(Generate_item) == VObjectType::paENDGENERATE)) {
break;
}
}
}
} else {
subSubInstances.push_back(subInstanceId);
}

for (auto subInstanceId : subSubInstances) {
NodeId childId;
Expand Down Expand Up @@ -1823,11 +1857,6 @@ void DesignElaboration::elaborateInstance_(
}
}
}
if (!elaborated) {
NetlistElaboration* nelab = new NetlistElaboration(m_compileDesign);
nelab->elaborateInstance(parent);
delete nelab;
}
}

void DesignElaboration::reportElaboration_() {
Expand Down
816 changes: 816 additions & 0 deletions tests/GenerateBlock2/GenerateBlock2.log
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1 change: 1 addition & 0 deletions tests/GenerateBlock2/GenerateBlock2.sl
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@@ -0,0 +1 @@
-parse -d uhdm -d coveruhdm -elabuhdm -d ast dut.sv -nobuiltin
21 changes: 21 additions & 0 deletions tests/GenerateBlock2/dut.sv
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@@ -0,0 +1,21 @@

module sub (output reg int_status);
endmodule

module dut ();
parameter p = 1'b1;
generate
if (p == 1'b1) begin : blk
end
endgenerate
generate
genvar loop_int;
wire [2:0] int_status;
for (loop_int = 0; loop_int < 2; loop_int = loop_int + 1)
begin : gen_blk
sub sub_i (
.int_status(int_status[loop_int])
);
end
endgenerate
endmodule
6 changes: 3 additions & 3 deletions third_party/tests/AmiqSimpleTestSuite/AmiqSimpleTestSuite.log
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Expand Up @@ -454,7 +454,7 @@ chandle_var 2
class_defn 645
class_typespec 17241
class_var 8981
constant 88736
constant 88900
constraint 13
continue_stmt 124
cover 30
Expand Down Expand Up @@ -504,7 +504,7 @@ named_fork 7
operation 23996
package 8
packed_array_typespec 8
param_assign 3226
param_assign 3390
parameter 5309
part_select 123
port 9
Expand All @@ -515,7 +515,7 @@ real_typespec 41
real_var 8
ref_module 5
ref_obj 102956
ref_typespec 56922
ref_typespec 57082
ref_var 4666
repeat 76
return_stmt 6983
Expand Down
6 changes: 3 additions & 3 deletions third_party/tests/CoresSweRVMP/CoresSweRVMP.log
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Expand Up @@ -76,9 +76,9 @@ Running: cd ${SURELOG_DIR}/build/regression/CoresSweRVMP/slpp_all/mp_preprocess;
[ 62%] Generating 3_rvjtag_tap.sv
[ 68%] Generating 4_dec_tlu_ctl.sv
[ 75%] Generating 5_lsu_bus_buffer.sv
[ 81%] Generating 7_axi4_to_ahb.sv
[ 87%] Generating 8_ifu_aln_ctl.sv
[ 93%] Generating 6_dbg.sv
[ 81%] Generating 6_dbg.sv
[ 87%] Generating 7_axi4_to_ahb.sv
[ 93%] Generating 8_ifu_aln_ctl.sv
[100%] Generating 9_tb_top.sv
[100%] Built target Parse
Surelog parsing status: 0
Expand Down
2 changes: 1 addition & 1 deletion third_party/tests/YosysDsp/YosysDsp.log
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Expand Up @@ -1278,8 +1278,8 @@
[INF:CP0335] ${SURELOG_DIR}/third_party/tests/YosysDsp/lfsr.v:124:2: Compile generate block "[email protected]_LFSR[23]".
[INF:CP0335] ${SURELOG_DIR}/third_party/tests/YosysDsp/shalfband.v:130:11: Compile generate block "[email protected]_TAP_ADJUSTMENT".
[INF:CP0335] ${SURELOG_DIR}/third_party/tests/YosysDsp/slowfil.v:101:3: Compile generate block "work@slowfil_fixedtaps.fir.genblk1".
[INF:CP0335] ${SURELOG_DIR}/third_party/tests/YosysDsp/slowfil_srl.v:103:2: Compile generate block "work@slowfil_srl_fixedtaps.fir.FIXED_TAP_READMEM".
[INF:CP0303] ${SURELOG_DIR}/third_party/tests/YosysDsp/slowfil_srl.v:49:1: Compile module "work@slowfil_srl".
[INF:CP0335] ${SURELOG_DIR}/third_party/tests/YosysDsp/slowfil_srl.v:103:2: Compile generate block "work@slowfil_srl_fixedtaps.fir.FIXED_TAP_READMEM".
[INF:CP0335] ${SURELOG_DIR}/third_party/tests/YosysDsp/slowfil_srl.v:150:39: Compile generate block "work@slowfil_srl_fixedtaps.fir.genblk2[1]".
[INF:CP0335] ${SURELOG_DIR}/third_party/tests/YosysDsp/slowfil_srl.v:150:39: Compile generate block "work@slowfil_srl_fixedtaps.fir.genblk2[2]".
[INF:CP0335] ${SURELOG_DIR}/third_party/tests/YosysDsp/slowfil_srl.v:150:39: Compile generate block "work@slowfil_srl_fixedtaps.fir.genblk2[3]".
Expand Down
2 changes: 1 addition & 1 deletion third_party/tests/ariane/Ariane.log
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Expand Up @@ -748,6 +748,7 @@ there are 1 more instances of this message.
[INF:CP0335] ${SURELOG_DIR}/third_party/tests/ariane/src/util/sram.sv:70:14: Compile generate block "work@ariane_testharness.i_sram.gen_cut[0].gen_mem".
[INF:CP0335] ${SURELOG_DIR}/third_party/tests/ariane/src/fpga-support/rtl/SyncSpRamBeNx64.sv:153:22: Compile generate block "work@ariane_testharness.i_sram.gen_cut[0].gen_mem.i_ram.g_oureg_byp".
[INF:CP0303] ${SURELOG_DIR}/third_party/tests/ariane/src/axi_node/src/axi_node_intf_wrap.sv:11:1: Compile module "work@axi_node_intf_wrap".
[INF:CP0303] ${SURELOG_DIR}/third_party/tests/ariane/src/axi_node/src/axi_node_intf_wrap.sv:11:1: Compile module "work@axi_node_intf_wrap".
[INF:CP0335] ${SURELOG_DIR}/third_party/tests/ariane/src/axi_node/src/axi_node_intf_wrap.sv:147:5: Compile generate block "work@ariane_testharness.i_axi_xbar.genblk1[0]".
[INF:CP0335] ${SURELOG_DIR}/third_party/tests/ariane/src/axi_node/src/axi_node_intf_wrap.sv:147:5: Compile generate block "work@ariane_testharness.i_axi_xbar.genblk1[1]".
[INF:CP0335] ${SURELOG_DIR}/third_party/tests/ariane/src/axi_node/src/axi_node_intf_wrap.sv:147:5: Compile generate block "work@ariane_testharness.i_axi_xbar.genblk1[2]".
Expand All @@ -758,7 +759,6 @@ there are 1 more instances of this message.
[INF:CP0335] ${SURELOG_DIR}/third_party/tests/ariane/src/axi_node/src/axi_node_intf_wrap.sv:147:5: Compile generate block "work@ariane_testharness.i_axi_xbar.genblk1[7]".
[INF:CP0335] ${SURELOG_DIR}/third_party/tests/ariane/src/axi_node/src/axi_node_intf_wrap.sv:147:5: Compile generate block "work@ariane_testharness.i_axi_xbar.genblk1[8]".
[INF:CP0335] ${SURELOG_DIR}/third_party/tests/ariane/src/axi_node/src/axi_node_intf_wrap.sv:147:5: Compile generate block "work@ariane_testharness.i_axi_xbar.genblk1[9]".
[INF:CP0303] ${SURELOG_DIR}/third_party/tests/ariane/src/axi_node/src/axi_node_intf_wrap.sv:11:1: Compile module "work@axi_node_intf_wrap".
[INF:CP0335] ${SURELOG_DIR}/third_party/tests/ariane/src/axi_node/src/axi_node_intf_wrap.sv:203:5: Compile generate block "work@ariane_testharness.i_axi_xbar.genblk2[0]".
[INF:CP0335] ${SURELOG_DIR}/third_party/tests/ariane/src/axi_node/src/axi_node_intf_wrap.sv:203:5: Compile generate block "work@ariane_testharness.i_axi_xbar.genblk2[1]".
[INF:CP0335] ${SURELOG_DIR}/third_party/tests/ariane/src/axi_node/src/axi_node.sv:265:1: Compile generate block "work@ariane_testharness.i_axi_xbar.axi_node_i._REVERSING_VALID_READY_MASTER[0]".
Expand Down
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