Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Jump to bottom

Bits and size support in gen stmt, late binding of signals #3986

Merged
merged 1 commit into from
Sep 24, 2024
Merged

Bits and size support in gen stmt, late binding of signals #3986

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
1 commit
Select commit
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
19 changes: 19 additions & 0 deletions .vscode/launch.json
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -369,6 +369,25 @@
}
]
},
{
"name": "Rggen",
"type": "cppdbg",
"request": "launch",
"program": "${workspaceFolder}/dbuild/bin/surelog",
"args": ["-f", "Rggen.sl"],
"stopAtEntry": false,
"cwd": "${workspaceFolder}/third_party/tests/rggen",
"environment": [],
"externalConsole": false,
"MIMode": "gdb",
"setupCommands": [
{
"description": "Enable pretty-printing for gdb",
"text": "-enable-pretty-printing",
"ignoreFailures": true
}
]
},
{
"name": "BlackParrotOOB",
"type": "cppdbg",
Expand Down
704 changes: 704 additions & 0 deletions tests/BitsInGenBlock/BitsInGenBlock.log
View file
Open in desktop

Large diffs are not rendered by default.

1 change: 1 addition & 0 deletions tests/BitsInGenBlock/BitsInGenBlock.sl
View file
Open in desktop
Original file line number Diff line number Diff line change
@@ -0,0 +1 @@
-parse -d uhdm -d coveruhdm -elabuhdm -d ast dut.sv -nobuiltin
31 changes: 31 additions & 0 deletions tests/BitsInGenBlock/dut.sv
View file
Open in desktop
Original file line number Diff line number Diff line change
@@ -0,0 +1,31 @@
module GOOD();

endmodule; // GOOD

module ibex_top (

output logic instr_req_o,
input logic instr_gnt_i,
output byte b
);



generate
if (1) begin

localparam int NumBufferBits = $bits({

instr_req_o, // 1 bit
instr_gnt_i, // 1 bit
b // 8 bits
});

if (NumBufferBits == 10) begin
GOOD good();
end

end
endgenerate

endmodule
8 changes: 2 additions & 6 deletions tests/HighLow/HighLow.log
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -298,7 +298,7 @@ AST_DEBUG_END
[INF:UH0706] Creating UHDM Model...
=== UHDM Object Stats Begin (Non-Elaborated Model) ===
begin 4
constant 42
constant 41
cont_assign 2
design 1
gen_if 4
Expand All @@ -320,7 +320,7 @@ sys_func_call 10
[INF:UH0707] Elaborating UHDM...
=== UHDM Object Stats Begin (Elaborated Model) ===
begin 4
constant 42
constant 41
cont_assign 3
design 1
gen_if 4
Expand Down Expand Up @@ -866,10 +866,7 @@ design: (work@top)
\_constant:
|vpiParent:
\_cont_assign: , line:12:10, endln:12:24
|vpiDecompile:2
|vpiSize:64
|UINT:2
|vpiConstType:9
|vpiLhs:
\_ref_obj: ([email protected]), line:12:10, endln:12:13
|vpiParent:
Expand Down Expand Up @@ -1064,7 +1061,6 @@ design: (work@top)
\_logic_typespec:
|vpiLeftRange:
\_constant:
|UINT:2
|vpiRightRange:
\_constant:
|UINT:1
Expand Down
2 changes: 1 addition & 1 deletion third_party/UHDM
Open in desktop
Submodule UHDM updated 1 files
+9 −1 templates/ExprEval.cpp
2 changes: 1 addition & 1 deletion third_party/tests/AzadiRTL/AzadiRTL.log
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -13904,7 +13904,7 @@ case_stmt 316
class_defn 8
class_typespec 4
class_var 3
constant 275929
constant 275928
cont_assign 15432
delay_control 8
design 1
Expand Down
12 changes: 6 additions & 6 deletions third_party/tests/CoresSweRVMP/CoresSweRVMP.log
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -64,20 +64,20 @@ Running: cd ${SURELOG_DIR}/build/regression/CoresSweRVMP/slpp_all/mp_preprocess;
-- Configuring done
-- Generating done
-- Build files have been written to: ${SURELOG_DIR}/build/regression/CoresSweRVMP/slpp_all/mp_preprocess
[ 6%] Generating 10_lsu_bus_intf.sv
[ 12%] Generating 11_ifu_bp_ctl.sv
[ 6%] Generating 15_exu.sv
[ 12%] Generating 14_mem_lib.sv
[ 18%] Generating 12_beh_lib.sv
[ 25%] Generating 13_ifu_mem_ctl.sv
[ 31%] Generating 14_mem_lib.sv
[ 37%] Generating 15_exu.sv
[ 31%] Generating 1_lsu_stbuf.sv
[ 37%] Generating 11_ifu_bp_ctl.sv
[ 43%] Generating 16_dec_decode_ctl.sv
[ 50%] Generating 1_lsu_stbuf.sv
[ 50%] Generating 10_lsu_bus_intf.sv
[ 56%] Generating 2_ahb_to_axi4.sv
[ 62%] Generating 3_rvjtag_tap.sv
[ 68%] Generating 4_dec_tlu_ctl.sv
[ 75%] Generating 5_lsu_bus_buffer.sv
[ 81%] Generating 6_dbg.sv
[ 87%] Generating 7_axi4_to_ahb.sv
[ 87%] Generating 6_dbg.sv
[ 93%] Generating 8_ifu_aln_ctl.sv
[100%] Generating 9_tb_top.sv
[100%] Built target Parse
Expand Down
2 changes: 1 addition & 1 deletion third_party/tests/Earlgrey_0_1/sim-icarus/Earlgrey_0_1.log
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -6244,7 +6244,7 @@ case_stmt 614
class_defn 8
class_typespec 4
class_var 3
constant 348744
constant 348743
cont_assign 47364
design 1
enum_const 2553
Expand Down
10 changes: 5 additions & 5 deletions third_party/tests/Earlgrey_Verilator_01_05_21/sim-icarus/Earlgrey_Verilator_01_05_21.log
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -14390,7 +14390,7 @@ part_select 4960
port 91788
range 167931
ref_module 5040
ref_obj 332702
ref_obj 332695
ref_typespec 453726
ref_var 174
return_stmt 429
Expand All @@ -14399,7 +14399,7 @@ string_var 19
struct_net 571
struct_typespec 24138
struct_var 1840
sys_func_call 500
sys_func_call 493
tagged_pattern 33133
task 9
typespec_member 68262
Expand Down Expand Up @@ -14427,7 +14427,7 @@ chandle_var 14
class_defn 8
class_typespec 4
class_var 3
constant 936087
constant 936086
cont_assign 147474
design 1
enum_const 31258
Expand Down Expand Up @@ -14475,7 +14475,7 @@ part_select 22451
port 224742
range 171087
ref_module 5040
ref_obj 1087996
ref_obj 1087989
ref_typespec 796720
ref_var 176
return_stmt 15514
Expand All @@ -14484,7 +14484,7 @@ string_var 36
struct_net 571
struct_typespec 24138
struct_var 2418
sys_func_call 2410
sys_func_call 2403
tagged_pattern 33523
task 18
typespec_member 68262
Expand Down
2 changes: 1 addition & 1 deletion third_party/tests/Earlgrey_Verilator_0_1/sim-verilator/Earlgrey_Verilator_0_1.log
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -5905,7 +5905,7 @@ chandle_var 11
class_defn 8
class_typespec 4
class_var 3
constant 325988
constant 325987
cont_assign 43470
design 1
enum_const 2451
Expand Down
4 changes: 2 additions & 2 deletions third_party/tests/IncompTitan/IncompTitan.log
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -5386,7 +5386,7 @@ property_inst 4
property_spec 479
range 75232
ref_module 2376
ref_obj 166321
ref_obj 166320
ref_typespec 167850
ref_var 74
return_stmt 137
Expand All @@ -5395,7 +5395,7 @@ string_typespec 10655
struct_net 147
struct_typespec 5521
struct_var 1295
sys_func_call 2746
sys_func_call 2745
tagged_pattern 7929
task 9
typespec_member 17886
Expand Down
8 changes: 4 additions & 4 deletions third_party/tests/NyuziProcessor/NyuziProcessor.log
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -943,14 +943,14 @@ part_select 435
port 3875
range 18477
ref_module 187
ref_obj 33534
ref_obj 33530
ref_typespec 138196
string_typespec 84
string_var 1
struct_net 81
struct_typespec 1093
struct_var 77
sys_func_call 2609
sys_func_call 2605
task 13
task_call 11
typespec_member 7460
Expand Down Expand Up @@ -1023,14 +1023,14 @@ part_select 1179
port 7457
range 18627
ref_module 187
ref_obj 90442
ref_obj 90438
ref_typespec 203147
string_typespec 84
string_var 1
struct_net 81
struct_typespec 1093
struct_var 135
sys_func_call 3571
sys_func_call 3567
task 26
task_call 22
typespec_member 7460
Expand Down
2 changes: 1 addition & 1 deletion third_party/tests/Opentitan/Earlgrey.log
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -25248,7 +25248,7 @@ case_stmt 336
class_defn 8
class_typespec 4
class_var 3
constant 217425
constant 217424
cont_assign 30746
design 1
enum_const 2021
Expand Down
2 changes: 1 addition & 1 deletion third_party/tests/Opentitan/Opentitan.log
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -4307,7 +4307,7 @@ chandle_var 2
class_defn 613
class_typespec 8828
class_var 22226
constant 252355
constant 252354
constraint 10
cont_assign 30814
continue_stmt 173
Expand Down
Loading