[Scala3][WIP] Scala3 testing I

src/test/scala-2/chiselTests/experimental/OpaqueTypeSpec.scala

@@ -115,12 +115,12 @@ object OpaqueTypeSpec {
   class Boxed[T <: Data](gen: T) extends MaybeBoxed[T] {
     def boxed = true
     lazy val elements = SeqMap("underlying" -> gen)
-    def underlying = elements.head._2
+    def underlying = elements.head._2.asInstanceOf[T]
   }
   class Unboxed[T <: Data](gen: T) extends MaybeBoxed[T] with OpaqueType {
     def boxed = false
     lazy val elements = SeqMap("" -> gen)
-    def underlying = elements.head._2
+    def underlying = elements.head._2.asInstanceOf[T]
   }
 
   class MaybeNoAsUInt(noAsUInt: Boolean) extends Record with OpaqueType {

src/test/scala-2/chiselTests/interface/Drivers.scala

@@ -5,7 +5,7 @@ import java.io.File
 import chisel3.RawModule
 import chisel3.stage.ChiselGeneratorAnnotation
 import circt.stage.{ChiselStage, FirtoolOption}
-import firrtl.AnnotationSeq
+import firrtl.{seqToAnnoSeq, AnnotationSeq}
 import firrtl.options.{StageError, StageUtils}
 import sys.process._
 

src/test/scala-2/chiselTests/simulator/SimulatorSpec.scala

@@ -5,7 +5,7 @@ import chisel3.layer.{block, Convention, Layer, LayerConfig}
 import chisel3.simulator._
 import org.scalatest.funspec.AnyFunSpec
 import org.scalatest.matchers.must.Matchers
-import org.scalatest.matchers.should.Matchers.convertToAnyShouldWrapper
+// import org.scalatest.matchers.should.Matchers.convertToStringShouldWrapperForVerb
 import svsim._
 
 class VerilatorSimulator(val workspacePath: String) extends Simulator[verilator.Backend] {

src/test/scala-2/circtTests/stage/ChiselStageSpec.scala → src/test/scala-2/chiselTests/stage/ChiselStageSpec.scala

@@ -123,12 +123,12 @@ object ChiselStageSpec {
   }
 
   class RecoverableErrorFakeSourceInfo extends RawModule {
-    implicit val info = SourceLine("Foo", 3, 10)
+    implicit val info: SourceLine = SourceLine("Foo", 3, 10)
     3.U >> -1
   }
 
   class ErrorCaughtByFirtool extends RawModule {
-    implicit val info = SourceLine("Foo", 3, 10)
+    implicit val info: SourceLine = SourceLine("Foo", 3, 10)
     val w = Wire(UInt(8.W))
   }
 

src/test/scala/chiselTests/AdderTree.scala

@@ -20,7 +20,7 @@ class AdderTreeTester(bitWidth: Int, numsToAdd: List[Int]) extends Module {
   val dut = Module(new AdderTree(genType, numsToAdd.size))
   dut.io.numIn := VecInit(numsToAdd.map(x => x.asUInt(bitWidth.W)))
   val sumCorrect = dut.io.numOut === (numsToAdd.reduce(_ + _) % (1 << bitWidth)).asUInt(bitWidth.W)
-  assert(sumCorrect)
+  chisel3.assert(sumCorrect)
   stop()
 }
 

src/test/scala-2/chiselTests/AutoClonetypeSpec.scala → src/test/scala/chiselTests/AutoClonetypeSpec.scala

@@ -344,7 +344,7 @@ class AutoClonetypeSpec extends AnyFlatSpec with Matchers {
     }
     emitCHIRRTL {
       new Module {
-        implicit val x = 8
+        implicit val x: Int = 8
         val in = IO(Input(new MyBundle))
         val out = IO(Output(new MyBundle))
         out := in

src/test/scala-2/chiselTests/BlackBox.scala → src/test/scala/chiselTests/BlackBox.scala

@@ -374,7 +374,7 @@ class BlackBoxSpec extends AnyFlatSpec with Matchers with ChiselSim with FileChe
     object A extends layer.Layer(layer.LayerConfig.Extract())
 
     sealed trait NoIo { this: BlackBox @nowarn("cat=deprecation") =>
-      final val io = IO(new Bundle {})
+      final val io = chisel3.IO(new Bundle {})
     }
 
     // No known layers
@@ -419,7 +419,7 @@ class BlackBoxSpec extends AnyFlatSpec with Matchers with ChiselSim with FileChe
     class Bar extends BlackBox {
       final val io = IO {
         new Bundle {
-          val a = Output(probe.Probe(Bool(), layers.Verification))
+          val a = Output(probe.Probe(Bool(), chisel3.layers.Verification))
         }
       }
     }
@@ -430,7 +430,7 @@ class BlackBoxSpec extends AnyFlatSpec with Matchers with ChiselSim with FileChe
     class Baz extends BlackBox(knownLayers = Seq(A)) {
       final val io = IO {
         new Bundle {
-          val a = Output(probe.Probe(Bool(), layers.Verification))
+          val a = Output(probe.Probe(Bool(), chisel3.layers.Verification))
         }
       }
     }

src/test/scala-2/chiselTests/BulkConnectSpec.scala → src/test/scala/chiselTests/BulkConnectSpec.scala

@@ -75,7 +75,7 @@ class BulkConnectSpec extends AnyPropSpec with Matchers {
       val io: MyBundle = IO(Flipped(new MyBundle))
 
       @nowarn("cat=deprecation")
-      val bb = Module(new BlackBox {
+      val bb = Module[BlackBox { def io: MyBundle }](new BlackBox {
         val io: MyBundle = IO(Flipped(new MyBundle))
       })
 

src/test/scala-2/chiselTests/Decoder.scala → src/test/scala/chiselTests/Decoder.scala

@@ -14,7 +14,7 @@ class Decoder(bitpats: List[String]) extends Module {
     val inst = Input(UInt(32.W))
     val matched = Output(Bool())
   })
-  io.matched := VecInit(bitpats.map(BitPat(_) === io.inst)).reduce(_ || _)
+  io.matched := VecInit(bitpats.map(BitPat(_) === io.inst).reduce(_ || _))
 }
 
 class DecoderTester(pairs: List[(String, String)]) extends Module {

src/test/scala/chiselTests/IntrinsicSpec.scala

@@ -5,6 +5,7 @@ package chiselTests
 import chisel3._
 import chisel3.experimental.{fromIntToIntParam, fromStringToStringParam}
 import circt.stage.ChiselStage
+import chisel3.experimental.{fromIntToIntParam, fromStringToStringParam}
 import org.scalatest.flatspec.AnyFlatSpec
 import org.scalatest.matchers.should.Matchers
 

src/test/scala-2/chiselTests/ModuleChoiceSpec.scala → src/test/scala/chiselTests/ModuleChoiceSpec.scala

@@ -34,8 +34,8 @@ class ModuleWithChoice[T <: Data](
   default: => FixedIOBaseModule[T]
 )(alternateImpls: Seq[(Case, () => FixedIOBaseModule[T])])
     extends Module {
-  val inst = ModuleChoice(default)(alternateImpls)
-  val io = IO(inst.cloneType)
+  val inst: T = ModuleChoice[T](default, alternateImpls)
+  val io:   T = IO(chiselTypeOf(inst))
   io <> inst
 }
 

src/test/scala-2/chiselTests/SIntOps.scala → src/test/scala/chiselTests/SIntOps.scala

@@ -202,13 +202,13 @@ class SIntOpsSpec extends AnyPropSpec with Matchers with ShiftRightWidthBehavior
   }
 
   property("Static right-shift should have a minimum width of 1") {
-    testShiftRightWidthBehavior(SInt)(chiselMinWidth = 1, firrtlMinWidth = 1)
+    testSIntShiftRightWidthBehavior(chiselMinWidth = 1, firrtlMinWidth = 1)
   }
 
   property("Static right-shift should have width of 0 in Chisel and 1 in FIRRTL with --use-legacy-width") {
     val args = Array("--use-legacy-width")
 
-    testShiftRightWidthBehavior(SInt)(chiselMinWidth = 0, firrtlMinWidth = 1, args = args)
+    testSIntShiftRightWidthBehavior(chiselMinWidth = 0, firrtlMinWidth = 1, args = args)
 
     // Focused test to show the mismatch
     class TestModule extends Module {

src/test/scala-2/chiselTests/SimLogSpec.scala → src/test/scala/chiselTests/SimLogSpec.scala

@@ -33,7 +33,7 @@ class SimLogSpec extends AnyFlatSpec with Matchers with FileCheck with ChiselSim
     class MyModule extends Module {
       val in = IO(Input(UInt(8.W)))
       val fd = SimLog.file("logfile.log")
-      fd.printf("in = %d\n", in)
+      // fd.printf("in = %d\n", in)
     }
     ChiselStage
       .emitCHIRRTL(new MyModule)

src/test/scala-2/chiselTests/UIntOps.scala → src/test/scala/chiselTests/UIntOps.scala

@@ -214,62 +214,100 @@ class UIntLitZeroWidthTester extends Module {
 }
 
 trait ShiftRightWidthBehavior extends WidthHelpers {
-  // The UInt and SInt objects don't share a type, so make one up that they can conform to structurally
-  type BitsFactory[T <: Bits] = {
-    def apply():         T
-    def apply(w: Width): T
+  def testSIntShiftRightWidthBehavior(chiselMinWidth: Int, firrtlMinWidth: Int, args: Iterable[String] = Nil): Unit = {
+    assertKnownWidth(4, args) {
+      val in = IO(Input(SInt(8.W)))
+      in >> 4
+    }
+    assertKnownWidth(chiselMinWidth, args) {
+      val in = IO(Input(SInt(8.W)))
+      in >> 8
+    }
+    assertKnownWidth(chiselMinWidth, args) {
+      val in = IO(Input(SInt(8.W)))
+      in >> 16
+    }
+    assertKnownWidth(chiselMinWidth, args) {
+      val in = IO(Input(SInt(0.W)))
+      in >> 8
+    }
+    assertKnownWidth(chiselMinWidth, args) {
+      val in = IO(Input(SInt(0.W)))
+      in >> 0
+    }
+    assertInferredWidth(4, args) {
+      val in = IO(Input(SInt(8.W)))
+      val w = WireInit(SInt(), in)
+      w >> 4
+    }
+    assertInferredWidth(firrtlMinWidth, args) {
+      val in = IO(Input(SInt(8.W)))
+      val w = WireInit(SInt(), in)
+      w >> 8
+    }
+    assertInferredWidth(firrtlMinWidth, args) {
+      val in = IO(Input(SInt(8.W)))
+      val w = WireInit(SInt(), in)
+      w >> 16
+    }
+    assertInferredWidth(firrtlMinWidth, args) {
+      val in = IO(Input(SInt(0.W)))
+      val w = WireInit(SInt(), in)
+      w >> 8
+    }
+    assertInferredWidth(firrtlMinWidth, args) {
+      val in = IO(Input(SInt(0.W)))
+      val w = WireInit(SInt(), in)
+      w >> 0
+    }
   }
-
-  def testShiftRightWidthBehavior[T <: Bits](
-    factory: BitsFactory[T]
-  )(chiselMinWidth: Int, firrtlMinWidth: Int, args: Iterable[String] = Nil): Unit = {
+  def testUIntShiftRightWidthBehavior(chiselMinWidth: Int, firrtlMinWidth: Int, args: Iterable[String] = Nil): Unit = {
     assertKnownWidth(4, args) {
-      val in = IO(Input(factory(8.W)))
+      val in = IO(Input(UInt(8.W)))
       in >> 4
     }
     assertKnownWidth(chiselMinWidth, args) {
-      val in = IO(Input(factory(8.W)))
+      val in = IO(Input(UInt(8.W)))
       in >> 8
     }
     assertKnownWidth(chiselMinWidth, args) {
-      val in = IO(Input(factory(8.W)))
+      val in = IO(Input(UInt(8.W)))
       in >> 16
     }
     assertKnownWidth(chiselMinWidth, args) {
-      val in = IO(Input(factory(0.W)))
+      val in = IO(Input(UInt(0.W)))
       in >> 8
     }
     assertKnownWidth(chiselMinWidth, args) {
-      val in = IO(Input(factory(0.W)))
+      val in = IO(Input(UInt(0.W)))
       in >> 0
     }
     assertInferredWidth(4, args) {
-      val in = IO(Input(factory(8.W)))
-      val w = WireInit(factory(), in)
+      val in = IO(Input(UInt(8.W)))
+      val w = WireInit(UInt(), in)
       w >> 4
     }
     assertInferredWidth(firrtlMinWidth, args) {
-      val in = IO(Input(factory(8.W)))
-      val w = WireInit(factory(), in)
+      val in = IO(Input(UInt(8.W)))
+      val w = WireInit(UInt(), in)
       w >> 8
     }
     assertInferredWidth(firrtlMinWidth, args) {
-      val in = IO(Input(factory(8.W)))
-      val w = WireInit(factory(), in)
+      val in = IO(Input(UInt(8.W)))
+      val w = WireInit(UInt(), in)
       w >> 16
     }
     assertInferredWidth(firrtlMinWidth, args) {
-      val in = IO(Input(factory(0.W)))
-      val w = WireInit(factory(), in)
+      val in = IO(Input(UInt(0.W)))
+      val w = WireInit(UInt(), in)
       w >> 8
     }
     assertInferredWidth(firrtlMinWidth, args) {
-      val in = IO(Input(factory(0.W)))
-      val w = WireInit(factory(), in)
+      val in = IO(Input(UInt(0.W)))
+      val w = WireInit(UInt(), in)
       w >> 0
     }
   }
-
 }
 
 class UIntOpsSpec extends AnyPropSpec with Matchers with LogUtils with ShiftRightWidthBehavior with ChiselSim {
@@ -551,13 +589,13 @@ class UIntOpsSpec extends AnyPropSpec with Matchers with LogUtils with ShiftRigh
   }
 
   property("Static right-shift should have a minimum width of 0") {
-    testShiftRightWidthBehavior(UInt)(chiselMinWidth = 0, firrtlMinWidth = 0)
+    testUIntShiftRightWidthBehavior(chiselMinWidth = 0, firrtlMinWidth = 0)
   }
 
   property("Static right-shift should have width of 0 in Chisel and 1 in FIRRTL with --use-legacy-width") {
     val args = Array("--use-legacy-width")
 
-    testShiftRightWidthBehavior(UInt)(chiselMinWidth = 0, firrtlMinWidth = 1, args = args)
+    testUIntShiftRightWidthBehavior(chiselMinWidth = 0, firrtlMinWidth = 1, args = args)
 
     // Focused test to show the mismatch
     class TestModule extends Module {

src/test/scala-2/chiselTests/naming/NamePluginSpec.scala → src/test/scala/chiselTests/naming/NamePluginSpec.scala

@@ -3,7 +3,6 @@
 package chiselTests.naming
 
 import chisel3._
-import chisel3.aop.Select
 import chisel3.experimental.prefix
 import chisel3.experimental.AffectsChiselName
 import chisel3.testing.scalatest.FileCheck

src/test/scala-2/chiselTests/naming/PrefixSpec.scala → src/test/scala/chiselTests/naming/PrefixSpec.scala

@@ -3,7 +3,6 @@
 package chiselTests.naming
 
 import chisel3._
-import chisel3.aop.Select
 import chisel3.experimental.{noPrefix, prefix, skipPrefix, AffectsChiselPrefix}
 import chisel3.testing.scalatest.FileCheck
 import circt.stage.ChiselStage

src/test/scala-2/chiselTests/stage/ChiselAnnotationsSpec.scala → src/test/scala/chiselTests/stage/ChiselAnnotationsSpec.scala

@@ -8,6 +8,7 @@ import chisel3.stage.{ChiselCircuitAnnotation, ChiselGeneratorAnnotation, Design
 import firrtl.options.OptionsException
 import org.scalatest.flatspec.AnyFlatSpec
 import org.scalatest.matchers.should.Matchers
+import firrtl.{annoSeqToSeq, seqToAnnoSeq, AnnotationSeq}
 
 class ChiselAnnotationsSpecFoo extends RawModule {
   val in = IO(Input(Bool()))

src/test/scala-2/chiselTests/testing/HasTestingDirectorySpec.scala → src/test/scala/chiselTests/testing/HasTestingDirectorySpec.scala

@@ -68,8 +68,6 @@ class HasTestingDirectorySpec extends AnyFlatSpec with Matchers {
       testingDirectory.getDirectory
     }
 
-    implicit val bar = implicitly[HasTestingDirectory]
-
     foo should be(foo)
 
   }

src/test/scala-2/circtTests/OutputDirAnnotationSpec.scala → src/test/scala/circtTests/OutputDirAnnotationSpec.scala

@@ -7,7 +7,7 @@ import circt.outputDir
 import circt.stage.ChiselStage
 import org.scalatest.funspec.AnyFunSpec
 import org.scalatest.matchers.should.Matchers
-import chiselTests.experimental.hierarchy.Utils
+// import chiselTests.experimental.hierarchy.Utils
 
 class OutputDirAnnotationSpec extends AnyFunSpec with Matchers {
   describe("output directory annotation works") {