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Ensure past intrinsics are emitted with an explicit clock #5291

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Merged
jackkoenig merged 2 commits into from
May 7, 2026
Merged

Ensure past intrinsics are emitted with an explicit clock #5291

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6528822
Ensure past intrinsics are emitted with an explicit clock
TaoBi22 May 7, 2026
d371506
Address review comment
TaoBi22 May 7, 2026
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2 changes: 1 addition & 1 deletion src/main/scala/chisel3/ltl/LTL.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -136,7 +136,7 @@ object Sequence extends SequenceObjIntf {
OpaqueSequence(LTLDelayIntrinsic(delay, None)(seq.inner))

protected def _past(seq: Sequence, delay: Int)(implicit sourceInfo: SourceInfo): Sequence =
OpaqueSequence(LTLPastIntrinsic(delay)(seq.inner))
OpaqueSequence(LTLPastIntrinsic(delay, Some(Module.clock))(seq.inner))
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protected def _pastClock(seq: Sequence, delay: Int, clock: Clock)(implicit sourceInfo: SourceInfo): Sequence =
OpaqueSequence(LTLPastIntrinsic(delay, Some(clock))(seq.inner))
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18 changes: 9 additions & 9 deletions src/test/scala/chiselTests/LTLSpec.scala
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Expand Up @@ -75,15 +75,15 @@ class LTLSpec extends AnyFlatSpec with Matchers with ChiselSim with FileCheck {
ChiselStage.emitSystemVerilog(new DelaysMod)
}

class PastMod extends RawModule {
class PastMod extends Module {
implicit val info: SourceInfo = SourceLine("Foo.scala", 1, 2)
val a, b = IO(Input(Bool()))
val clock = IO(Input(Clock()))
val myClock = IO(Input(Clock()))
val s0: Sequence = a.past()
val s1: Sequence = a.past(3)
val s2: Sequence = Sequence.past(b, 2)
val s3: Sequence = a.past(clock)
val s4: Sequence = a.past(2, clock)
val s3: Sequence = a.past(myClock)
val s4: Sequence = a.past(2, myClock)
}
it should "support sequence past operations" in {
val sourceLoc = "@[Foo.scala 1:2]"
Expand All @@ -92,12 +92,12 @@ class LTLSpec extends AnyFlatSpec with Matchers with ChiselSim with FileCheck {
.fileCheck()(
s"""|CHECK: input a : UInt<1>
|CHECK: input b : UInt<1>
|CHECK: input clock : Clock
|CHECK: intrinsic(circt_ltl_past<delay = 1> : UInt<1>, a) $sourceLoc
|CHECK: intrinsic(circt_ltl_past<delay = 3> : UInt<1>, a) $sourceLoc
|CHECK: intrinsic(circt_ltl_past<delay = 2> : UInt<1>, b) $sourceLoc
|CHECK: input myClock : Clock
|CHECK: intrinsic(circt_ltl_past<delay = 1> : UInt<1>, a, clock) $sourceLoc
|CHECK: intrinsic(circt_ltl_past<delay = 2> : UInt<1>, a, clock) $sourceLoc
|CHECK: intrinsic(circt_ltl_past<delay = 3> : UInt<1>, a, clock) $sourceLoc
|CHECK: intrinsic(circt_ltl_past<delay = 2> : UInt<1>, b, clock) $sourceLoc
|CHECK: intrinsic(circt_ltl_past<delay = 1> : UInt<1>, a, myClock) $sourceLoc
|CHECK: intrinsic(circt_ltl_past<delay = 2> : UInt<1>, a, myClock) $sourceLoc
|""".stripMargin
)
}
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