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Update RgGen sample #7980

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Update RgGen sample #7980

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23 changes: 15 additions & 8 deletions generators/rggen
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Original file line number Diff line number Diff line change
Expand Up @@ -130,9 +130,10 @@ module rggen;
logic [1:0] register_13_bit_field_8;
logic register_13_bit_field_8_hw_write_enable;
logic [1:0] register_13_bit_field_8_hw_write_data;
logic register_14_bit_field_0;
logic register_15_bit_field_0;
rggen_bus_if #(8, 32) register_17_bus_if();
logic register_16_bit_field_0;
logic [15:0] register_17_bit_field_0;
rggen_bus_if #(8, 32) register_19_bus_if();

always_comb begin
register_2_bit_field_0 = register_0_bit_field_0;
Expand Down Expand Up @@ -168,7 +169,7 @@ module rggen;
register_13_bit_field_7_hw_set = register_13_bit_field_3_read_trigger;
register_13_bit_field_8_hw_write_enable = register_13_bit_field_3_write_trigger;
register_13_bit_field_8_hw_write_data = register_13_bit_field_3;
register_14_bit_field_0 = register_0_bit_field_0[0];
register_15_bit_field_0 = register_0_bit_field_0[0];
end

block_0 #(
Expand Down Expand Up @@ -293,16 +294,22 @@ module rggen;
.o_register_13_bit_field_8 (register_13_bit_field_8 ),
.i_register_13_bit_field_8_hw_write_enable (register_13_bit_field_8_hw_write_enable ),
.i_register_13_bit_field_8_hw_write_data (register_13_bit_field_8_hw_write_data ),
.i_register_14_bit_field_0 (register_14_bit_field_0 ),
.o_register_15_bit_field_0 (register_15_bit_field_0 ),
.register_17_bus_if (register_17_bus_if )
.i_register_14_bit_field_0_up (register_0_bit_field_0[0] ),
.i_register_14_bit_field_0_down (register_0_bit_field_1[0] ),
.i_register_14_bit_field_0_clear (register_3_bit_field_3_trigger[0] ),
.o_register_14_bit_field_0 (register_14_bit_field_0 ),
.i_register_14_bit_field_1_up (register_0_bit_field_0[0] ),
.i_register_14_bit_field_1_down (register_0_bit_field_1[0] ),
.i_register_15_bit_field_0 (register_15_bit_field_0 ),
.o_register_16_bit_field_0 (register_16_bit_field_0 ),
.o_register_17_bit_field_0 (register_17_bit_field_0 ),
.register_19_bus_if (register_19_bus_if )
);


rggen_apb_bridge u_bridge (
.i_clk (clk ),
.i_rst_n (rst_n ),
.bus_if (register_17_bus_if ),
.bus_if (register_19_bus_if ),
.apb_if (apb_if[1] )
);

Expand Down