Remove 16.15--property-iff-uvm-fail.sv

[wsnyder]

The 16.15--property-iff-uvm-fail.sv test contains many missing pin connections. Verilator treats those as warnings and manages to compile it, and it even $finish-es. The test however is looking for a simulation-time fail because it assumes that clocks etc were hooked up correctly (which they were not). The tools that were passing on this test were only parsing not simulating.

I don't see value in fixing the test given other tests cover this without using UVM (16.12--property-disable-iff.sv), so just removing.

[github-actions]

Changes In Tests

Tool	New Failures	New Passes	Added	Removed	Not Affected
Verilator	0	0	0	1	5080
moore_parse	0	0	0	0	4922
SynligYosys	0	0	0	0	4734
Yosys	0	0	0	0	4735
VeribleExtractor	0	0	0	0	4922
Icarus	0	0	0	1	5080
Verible	0	0	0	0	4922
Odin	0	0	0	0	5013
circt_verilog	0	0	0	0	5075
sv_parser	0	0	0	0	5013
Slang_parse	0	0	0	0	5013
Surelog	0	0	0	0	5076
moore	0	0	0	0	5013
tree_sitter_verilog	0	0	0	0	4922
Slang	0	0	0	0	5076
tree_sitter_systemverilog	4	0	0	0	4915
Sv2v_zachjs	0	0	0	0	5076
yosys_slang	0	0	0	0	4272

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