Port to f28069 launch pad

els-f280049c/.ccsproject

@@ -7,11 +7,12 @@
 	<deviceEndianness value="little"/>
 	<codegenToolVersion value="18.12.1.LTS"/>
 	<isElfFormat value="false"/>
-	<connection value="common/targetdb/connections/TIXDS110_Connection.xml"/>
+	<connection value="common/targetdb/connections/TIXDS100v2_Connection.xml"/>
 	<linkerCommandFile value="280049C_RAM_lnk.cmd"/>
 	<rts value="libc.a"/>
 	<createSlaveProjects value=""/>
 	<templateProperties value="id=com.ti.common.project.core.emptyProjectWithMainTemplate"/>
 	<filesToOpen value="main.c"/>
 	<isTargetManual value="false"/>
+	<sourceLookupPath value=""/>
 </projectOptions>

els-f280049c/.gitignore

@@ -1,3 +1,5 @@
 /Release/
 /Debug/
 /.launches/
+/F2806x-Debug/
+/F2806x-Release/

els-f280049c/.settings/org.eclipse.core.resources.prefs

@@ -5,11 +5,39 @@ encoding//Debug/device_support_f28004x/headers/cmd/subdir_rules.mk=UTF-8
 encoding//Debug/device_support_f28004x/headers/cmd/subdir_vars.mk=UTF-8
 encoding//Debug/device_support_f28004x/headers/source/subdir_rules.mk=UTF-8
 encoding//Debug/device_support_f28004x/headers/source/subdir_vars.mk=UTF-8
+encoding//Debug/device_support_f2806x/common/source/subdir_rules.mk=UTF-8
+encoding//Debug/device_support_f2806x/common/source/subdir_vars.mk=UTF-8
+encoding//Debug/device_support_f2806x/headers/cmd/subdir_rules.mk=UTF-8
+encoding//Debug/device_support_f2806x/headers/cmd/subdir_vars.mk=UTF-8
+encoding//Debug/device_support_f2806x/headers/source/subdir_rules.mk=UTF-8
+encoding//Debug/device_support_f2806x/headers/source/subdir_vars.mk=UTF-8
 encoding//Debug/makefile=UTF-8
 encoding//Debug/objects.mk=UTF-8
 encoding//Debug/sources.mk=UTF-8
 encoding//Debug/subdir_rules.mk=UTF-8
 encoding//Debug/subdir_vars.mk=UTF-8
+encoding//F2806x-Debug/device_support_f2806x/common/source/subdir_rules.mk=UTF-8
+encoding//F2806x-Debug/device_support_f2806x/common/source/subdir_vars.mk=UTF-8
+encoding//F2806x-Debug/device_support_f2806x/headers/cmd/subdir_rules.mk=UTF-8
+encoding//F2806x-Debug/device_support_f2806x/headers/cmd/subdir_vars.mk=UTF-8
+encoding//F2806x-Debug/device_support_f2806x/headers/source/subdir_rules.mk=UTF-8
+encoding//F2806x-Debug/device_support_f2806x/headers/source/subdir_vars.mk=UTF-8
+encoding//F2806x-Debug/makefile=UTF-8
+encoding//F2806x-Debug/objects.mk=UTF-8
+encoding//F2806x-Debug/sources.mk=UTF-8
+encoding//F2806x-Debug/subdir_rules.mk=UTF-8
+encoding//F2806x-Debug/subdir_vars.mk=UTF-8
+encoding//F2806x-Release/device_support_f2806x/common/source/subdir_rules.mk=UTF-8
+encoding//F2806x-Release/device_support_f2806x/common/source/subdir_vars.mk=UTF-8
+encoding//F2806x-Release/device_support_f2806x/headers/cmd/subdir_rules.mk=UTF-8
+encoding//F2806x-Release/device_support_f2806x/headers/cmd/subdir_vars.mk=UTF-8
+encoding//F2806x-Release/device_support_f2806x/headers/source/subdir_rules.mk=UTF-8
+encoding//F2806x-Release/device_support_f2806x/headers/source/subdir_vars.mk=UTF-8
+encoding//F2806x-Release/makefile=UTF-8
+encoding//F2806x-Release/objects.mk=UTF-8
+encoding//F2806x-Release/sources.mk=UTF-8
+encoding//F2806x-Release/subdir_rules.mk=UTF-8
+encoding//F2806x-Release/subdir_vars.mk=UTF-8
 encoding//Release/device_support_f28004x/common/source/subdir_rules.mk=UTF-8
 encoding//Release/device_support_f28004x/common/source/subdir_vars.mk=UTF-8
 encoding//Release/device_support_f28004x/headers/cmd/subdir_rules.mk=UTF-8

els-f280049c/28069_RAM_lnk.cmd

@@ -0,0 +1,174 @@
+/*
+// TI File $Revision: /main/3 $
+// Checkin $Date: March 3, 2011   13:45:43 $
+//###########################################################################
+//
+// FILE:    28069_RAM_lnk.cmd
+//
+// TITLE:   Linker Command File For F28069 examples that run out of RAM
+//
+//          This ONLY includes all SARAM blocks on the F28069 device.
+//          This does not include flash or OTP.
+//
+//          Keep in mind that L0,L1,L2,L3 and L4 are protected by the code
+//          security module.
+//
+//          What this means is in most cases you will want to move to
+//          another memory map file which has more memory defined.
+//
+//###########################################################################
+// $TI Release: $ 
+// $Release Date: $ 
+//###########################################################################
+*/
+
+/* ======================================================
+// For Code Composer Studio V2.2 and later
+// ---------------------------------------
+// In addition to this memory linker command file,
+// add the header linker command file directly to the project.
+// The header linker command file is required to link the
+// peripheral structures to the proper locations within
+// the memory map.
+//
+// The header linker files are found in <base>\F2806x_headers\cmd
+//
+// For BIOS applications add:      F2806x_Headers_BIOS.cmd
+// For nonBIOS applications add:   F2806x_Headers_nonBIOS.cmd
+========================================================= */
+
+/* ======================================================
+// For Code Composer Studio prior to V2.2
+// --------------------------------------
+// 1) Use one of the following -l statements to include the
+// header linker command file in the project. The header linker
+// file is required to link the peripheral structures to the proper
+// locations within the memory map                                    */
+
+/* Uncomment this line to include file only for non-BIOS applications */
+/* -l F2806x_Headers_nonBIOS.cmd */
+
+/* Uncomment this line to include file only for BIOS applications */
+/* -l F2806x_Headers_BIOS.cmd */
+
+/* 2) In your project add the path to <base>\F2806x_headers\cmd to the
+   library search path under project->build options, linker tab,
+   library search path (-i).
+/*========================================================= */
+
+/* Define the memory block start/length for the F2806x
+   PAGE 0 will be used to organize program sections
+   PAGE 1 will be used to organize data sections
+
+   Notes:
+         Memory blocks on F28069 are uniform (ie same
+         physical memory) in both PAGE 0 and PAGE 1.
+         That is the same memory region should not be
+         defined for both PAGE 0 and PAGE 1.
+         Doing so will result in corruption of program
+         and/or data.
+
+         Contiguous SARAM memory blocks can be combined
+         if required to create a larger memory block.
+*/
+
+MEMORY
+{
+PAGE 0 :
+   /* BEGIN is used for the "boot to SARAM" bootloader mode   */
+
+   BEGIN       : origin = 0x000000, length = 0x000002
+   RAMM0       : origin = 0x000050, length = 0x0003B0
+   RAML0_L3    : origin = 0x008000, length = 0x002000	 /* RAML0-3 combined for size of .text */
+   														 /* in Example_F2806xSWPrioritezedInterrupts */
+   RESET       : origin = 0x3FFFC0, length = 0x000002
+   FPUTABLES   : origin = 0x3FD860, length = 0x0006A0	 /* FPU Tables in Boot ROM */
+   IQTABLES    : origin = 0x3FDF00, length = 0x000B50    /* IQ Math Tables in Boot ROM */
+   IQTABLES2   : origin = 0x3FEA50, length = 0x00008C    /* IQ Math Tables in Boot ROM */
+   IQTABLES3   : origin = 0x3FEADC, length = 0x0000AA	 /* IQ Math Tables in Boot ROM */
+
+   BOOTROM    : origin = 0x3FF3B0, length = 0x000C10
+
+
+PAGE 1 :
+
+   BOOT_RSVD   : origin = 0x000002, length = 0x00004E     /* Part of M0, BOOT rom will use this for stack */
+   RAMM1       : origin = 0x000400, length = 0x000400     /* on-chip RAM block M1 */
+   RAML4       : origin = 0x00A000, length = 0x002000     /* on-chip RAM block L4 */
+   RAML5       : origin = 0x00C000, length = 0x002000     /* on-chip RAM block L5 */
+   RAML6       : origin = 0x00E000, length = 0x002000     /* on-chip RAM block L6 */
+   RAML7       : origin = 0x010000, length = 0x002000     /* on-chip RAM block L7 */
+   RAML8       : origin = 0x012000, length = 0x002000     /* on-chip RAM block L8 */
+   USB_RAM     : origin = 0x040000, length = 0x000800     /* USB RAM		  */
+}
+
+
+SECTIONS
+{
+   /* Setup for "boot to SARAM" mode:
+      The codestart section (found in DSP28_CodeStartBranch.asm)
+      re-directs execution to the start of user code.  */
+   codestart        : > BEGIN,      PAGE = 0
+
+   ramfuncs         : > RAMM0,      PAGE = 0   
+
+   .text            : > RAML0_L3,   PAGE = 0	
+   .cinit           : > RAMM0,      PAGE = 0
+   .pinit           : > RAMM0,      PAGE = 0
+   .switch          : > RAMM0,      PAGE = 0
+   .reset           : > RESET,      PAGE = 0, TYPE = DSECT /* not used, */
+
+   .stack           : > RAMM1,      PAGE = 1
+   .ebss            : > RAML4,      PAGE = 1
+   .econst          : > RAML4,      PAGE = 1
+   .esysmem         : > RAML4,      PAGE = 1
+
+   IQmath           : > RAML0_L3,   PAGE = 0
+   IQmathTables     : > IQTABLES,   PAGE = 0, TYPE = NOLOAD
+
+   /* Allocate FPU math areas: */
+   FPUmathTables    : > FPUTABLES,  PAGE = 0, TYPE = NOLOAD
+
+   DMARAML5	        : > RAML5,      PAGE = 1
+   DMARAML6	        : > RAML6,      PAGE = 1
+   DMARAML7	        : > RAML7,      PAGE = 1
+   DMARAML8	        : > RAML8,      PAGE = 1   
+
+  /* Uncomment the section below if calling the IQNexp() or IQexp()
+      functions from the IQMath.lib library in order to utilize the
+      relevant IQ Math table in Boot ROM (This saves space and Boot ROM
+      is 1 wait-state). If this section is not uncommented, IQmathTables2
+      will be loaded into other memory (SARAM, Flash, etc.) and will take
+      up space, but 0 wait-state is possible.
+   */
+   /*
+   IQmathTables2    : > IQTABLES2, PAGE = 0, TYPE = NOLOAD
+   {
+
+              IQmath.lib<IQNexpTable.obj> (IQmathTablesRam)
+
+   }
+   */
+   /* Uncomment the section below if calling the IQNasin() or IQasin()
+      functions from the IQMath.lib library in order to utilize the
+      relevant IQ Math table in Boot ROM (This saves space and Boot ROM
+      is 1 wait-state). If this section is not uncommented, IQmathTables2
+      will be loaded into other memory (SARAM, Flash, etc.) and will take
+      up space, but 0 wait-state is possible.
+   */
+   /*
+   IQmathTables3    : > IQTABLES3, PAGE = 0, TYPE = NOLOAD
+   {
+
+              IQmath.lib<IQNasinTable.obj> (IQmathTablesRam)
+
+   }
+   */
+
+}
+
+/*
+//===========================================================================
+// End of file.
+//===========================================================================
+*/

els-f280049c/Configuration.h

@@ -29,7 +29,6 @@
 
 
 
-
 //================================================================================
 //                                  LEADSCREW
 //
@@ -123,12 +122,18 @@
 //
 // Define which hardware you're using:
 //
-//  1 - LaunchXL F280049C with ELS BoostXL v1
-//  2 - LaunchXL F280049C with ELS BoostXL v2
+//  1 - ELS BoostXL v1
+//  2 - ELS BoostXL v2
+//  3 - ELS BoostXL v2.1 (with SPIClk Modification)
 //================================================================================
 
 // See hardware version table above
-#define HARDWARE_VERSION 2
+#define HARDWARE_VERSION 3
+
+//Configure which LauchPad board we are targeting
+//  Preference is to set these in Build Configuration Predefined Symbols
+//#define TARGET_F28004X
+//#define TARGET_F2806X
 
 
 
@@ -143,6 +148,9 @@
 // and direction keys are ignored.
 //#define IGNORE_ALL_KEYS_WHEN_RUNNING
 
+// Store the state of the machine in EEPROM and restore on power up
+#define ENABLE_STORED_STATE
+
 
 
 
@@ -177,7 +185,12 @@
 #define RPM_CALC_RATE_HZ 2
 
 // Microprocessor system clock
+#ifdef TARGET_F28004X
 #define CPU_CLOCK_MHZ 100
+#endif
+#ifdef TARGET_F2806X
+#define CPU_CLOCK_MHZ 90
+#endif
 #define CPU_CLOCK_HZ (CPU_CLOCK_MHZ * 1000000)
 
 

els-f280049c/ControlPanel.cpp

@@ -37,10 +37,10 @@
 
 
 // Lower the TM1638 CS (STB) line
-#define CS_ASSERT GpioDataRegs.GPBCLEAR.bit.GPIO33 = 1
+#define CS_ASSERT GpioDataRegs.GPBCLEAR.bit.DISPLAY_CS = 1
 
 // Raise the TM1638 CS (STB) line
-#define CS_RELEASE GpioDataRegs.GPBSET.bit.GPIO33 = 1
+#define CS_RELEASE GpioDataRegs.GPBSET.bit.DISPLAY_CS = 1
 
 
 ControlPanel :: ControlPanel(SPIBus *spiBus)
@@ -60,9 +60,14 @@ void ControlPanel :: initHardware(void)
 {
     EALLOW;
 
-    // use GPIO33 as the chip select so we can control it ourselves
-    GpioCtrlRegs.GPBMUX1.bit.GPIO33 = 0x0;      // SELECT GPIO33
-    GpioCtrlRegs.GPBDIR.bit.GPIO33 = 1;         // output
+    // use a GPIO as the chip select so we can control it ourselves
+#ifdef TARGET_F28004X
+    GpioCtrlRegs.GPBMUX1.bit.DISPLAY_CS = 0x0;      // SELECT GPIO
+#endif
+#ifdef TARGET_F2806X
+    GpioCtrlRegs.GPBMUX2.bit.DISPLAY_CS = 0x0;      // SELECT GPIO
+#endif
+    GpioCtrlRegs.GPBDIR.bit.DISPLAY_CS = 1;         // output
     CS_RELEASE;                                 // set it to high
 
     EDIS;
@@ -237,6 +242,7 @@ KEY_REG ControlPanel :: getKeys()
 {
     KEY_REG newKeys;
     static KEY_REG noKeys;
+    noKeys.all = 0;
 
     configureSpiBus();
 

els-f280049c/ControlPanel.h

@@ -29,7 +29,14 @@
 
 #include "F28x_Project.h"
 #include "SPIBus.h"
-
+#include "Configuration.h"
+
+#ifdef TARGET_F28004X
+#define DISPLAY_CS GPIO33
+#endif
+#ifdef TARGET_F2806X
+#define DISPLAY_CS GPIO52
+#endif
 
 #define ZERO    0b1111110000000000 // 0
 #define ONE     0b0110000000000000 // 1

els-f280049c/Debug.cpp

@@ -37,11 +37,11 @@ void Debug :: initHardware( void )
 {
     // set up GPIO pins as output for debugging
     EALLOW;
-    GpioCtrlRegs.GPAMUX1.bit.GPIO2 = 0;
-    GpioCtrlRegs.GPADIR.bit.GPIO2 = 1;
-    GpioDataRegs.GPACLEAR.bit.GPIO2 = 1;
-    GpioCtrlRegs.GPAMUX1.bit.GPIO3 = 0;
-    GpioCtrlRegs.GPADIR.bit.GPIO3 = 1;
-    GpioDataRegs.GPACLEAR.bit.GPIO3 = 1;
+    GpioCtrlRegs.GPAMUX1.bit.DEBUG1 = 0;
+    GpioCtrlRegs.GPADIR.bit.DEBUG1 = 1;
+    GpioDataRegs.GPACLEAR.bit.DEBUG1 = 1;
+    GpioCtrlRegs.GPAMUX1.bit.DEBUG2 = 0;
+    GpioCtrlRegs.GPADIR.bit.DEBUG2 = 1;
+    GpioDataRegs.GPACLEAR.bit.DEBUG2 = 1;
     EDIS;
 }