Basic Virtual Memory Implementation Fixes & Improvements #165

nemecad · 2025-09-04T10:53:57Z

This PR addresses some previous feedback, most notably:

Set-associative TLB (machine::TLB): Implements a set-associative Translation Lookaside Buffer (TLB) frontend over physical memory, handling virtual to physical translation, flush, and replacement policy.
Pluggable Replacement Policies (machine::TLBPolicy): Abstract TLB replacement policy interface & implementations (RAND, LRU, LFU, PLRU) for set-associative tables.
SV32 Page-Table Walker (machine::PageTableWalker): Performs multi-level page-table walks (SV32) in memory to resolve a virtual address to a physical one.
Sv32Pte Bitfield Helpers (sv32.h): SV32-specific definitions: page-table entry (PTE) bitfields, shifts/masks, and PTE to physical address helpers.
VirtualAddress (virtual_address.h): Lightweight VirtualAddress wrapper offering raw access, alignment checks, arithmetic, and comparisons.
Add supervisor CSRs and sstatus handling: supervisor CSRs (sstatus, stvec, sscratch, sepc, scause, stval, satp) and a write handler that presents sstatus as a masked view of mstatus so supervisor-visible bits stay in sync.
Store current privilege level in CoreState: tracking of the hart's current privilege level in CoreState so exception/return handling and visualization can read/update it from the central CoreState structure.

Tests:

Add SV32 page-table + TLB integration tests: a set of small assembly tests that exercise the SV32 page-table walker, SATP enablement and the new TLB code. The tests create a root page table and map a virtual page at 0xC4000000, then exercise several scenarios. The tests verify page-table walker behaviour, SATP switching and TLB caching/flush logic. Tests were written based on the consultation.

UI Components:

Show current privilege level in core state view:

Virtual memory configuration to NewDialog:

TLB visualization and statistics dock:

VM toggle and "As CPU" memory access view:

src/gui/CMakeLists.txt

src/gui/dialogs/new/newdialog.cpp

src/gui/windows/tlb/tlbview.cpp

src/gui/windows/tlb/tlbview.h

src/machine/CMakeLists.txt

src/machine/machine.cpp

src/machine/machine.h

src/machine/machineconfig.cpp

src/machine/memory/frontend_memory.cpp

src/machine/memory/virtual/sv32.h

jdupak · 2025-09-28T18:14:08Z

I am getting this weird zoom.

jdupak · 2025-09-28T18:14:47Z

Notice that address sanitizer is failing in CI.

jdupak · 2025-09-28T18:15:58Z

src/gui/windows/tlb/tlbview.h

+        void tlb_update(unsigned way, unsigned set, bool valid, unsigned asid, quint64 vpn, quint64 phys, bool write);
+
+private:
+    const machine::TLB *tlb;


Who owns this pointer?

jdupak · 2025-09-28T18:17:38Z

src/machine/memory/tlb/tlb.h

+#include <cstdint>
+
+namespace machine {
+enum TLBType { PROGRAM, DATA };


Why does LTB need to know this?

ppisa · 2025-09-29T08:51:35Z

@jdupak thanks for review of interfacing to the memory model architecture.

ppisa · 2025-09-29T08:51:45Z

From my side, the changes to the processor pipeline diagram has been applied directly to the SVG files (src/gui/windows/coreview/schemas), but current design uses DRAW.IO source (extras/core_graphics) as the authoritative source of the pipeline visualization and SVGs are generated from this file. So the commit with SVG change should include extras/core_graphics/diagram.drawio change as well or extras/core_graphics/diagram.drawio change should be commit before SVG files regeneration commit. In long term, I would lean to single SVG file with tags for conditional rendering, but we have not got to that state yet and current solution implemented by @jdupak is based on DRAW.IO and exports controlled by tagging (some documentation there docs/developer/coreview-graphics/using-drawio-diagram.md).

ppisa · 2025-09-29T08:55:46Z

For memory view, I would not complicate it with Show virtual checkbox. I would use only switching between As CPU (VMA), Cached and Raw.

nemecad · 2025-10-05T19:38:26Z

@ppisa @jdupak Thank you for your detailed feedback. I appreciate it and have made some changes based on your review. I would be grateful for any further feedback.

This resolves the incorrect zoom behavior.

Add tracking of the hart's current privilege level to the core state so code handling exceptions/returns and visualization can read/update it from the central CoreState structure.

Add supervisor CSRs (sstatus, stvec, sscratch, sepc, scause, stval, satp) and a write handler that presents sstatus as a masked view of mstatus so supervisor-visible bits stay in sync.

jdupak · 2025-10-19T14:49:24Z

tests/vm_assmebly/vm_template.s

There is a typo in the dir name

jdupak · 2025-10-19T14:50:16Z

tests/vm_assmebly/vm_template.s

There is no cmake logic to run these tests. I think we want to run them as cli tests.

Add privilege level mapping to the GUI so the current hart privilege (UNPRIV, SUPERV, HYPERV, MACHINE) is displayed in core state visualization.

Extend NewDialog with controls for virtual memory setup, including TLB number of sets, associativity, and replacement policy.

Introduce new components for displaying and tracking TLB state similar to cache. TLBViewBlock and TLBAddressBlock render per-set and per-way TLB contents, updated on tlb_update signals. TLBViewScene assembles these views based on associativity. TLBDock integrates into the GUI, showing hit/miss counts, memory accesses, stall cycles, hit rate, and speed improvement, with live updates from the TLB.

Introduce an "As CPU (VMA)" access option in the cached access selector to render memory contents as observed by the CPU through the frontend interface.

Add a set of small assembly tests that exercise the SV32 page-table walker, SATP enablement and the new TLB code. The tests create a root page table and map a virtual page at 0xC4000000, then exercise several scenarios. The tests verify page-table walker behaviour, SATP switching and TLB caching/flush logic. Tests were written based on the consultation.

jdupak · 2025-10-19T16:16:39Z

I pushed some slight edits. Barring the issue with new tests not being run I am fine with merging this.

jdupak self-requested a review September 28, 2025 17:17

jdupak reviewed Sep 28, 2025

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nemecad force-pushed the feature/sv32-vm-tlb-ptw-cleanup branch 5 times, most recently from 0bb04d1 to ca4300b Compare October 5, 2025 19:16

ppisa mentioned this pull request Oct 10, 2025

CLI: bugfix and improvements #166

Closed

jdupak and others added 4 commits October 19, 2025 16:29

Fix deprecation warnings for custom literals

2602c1e

GUI: fix zoom scaling issue

82aaf4e

This resolves the incorrect zoom behavior.

Machine: store current privilege level in CoreState

6c6c7da

Add tracking of the hart's current privilege level to the core state so code handling exceptions/returns and visualization can read/update it from the central CoreState structure.

Machine: add supervisor CSRs and sstatus handling

363141c

Add supervisor CSRs (sstatus, stvec, sscratch, sepc, scause, stval, satp) and a write handler that presents sstatus as a masked view of mstatus so supervisor-visible bits stay in sync.

jdupak force-pushed the feature/sv32-vm-tlb-ptw-cleanup branch from ca4300b to a6cbf71 Compare October 19, 2025 14:48

jdupak reviewed Oct 19, 2025

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tests/vm_assmebly/vm_template.s

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There is a typo in the dir name

jdupak reviewed Oct 19, 2025

View reviewed changes

tests/vm_assmebly/vm_template.s

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There is no cmake logic to run these tests. I think we want to run them as cli tests.

jdupak and others added 6 commits October 19, 2025 18:11

Machine: add TLB with policies and add SV32 page-table walker

2d5db0a

GUI: show current privilege level in core state view

d7ff20e

Add privilege level mapping to the GUI so the current hart privilege (UNPRIV, SUPERV, HYPERV, MACHINE) is displayed in core state visualization.

GUI: add virtual memory configuration to NewDialog

bdfdea1

Extend NewDialog with controls for virtual memory setup, including TLB number of sets, associativity, and replacement policy.

GUI: add "As CPU (VMA)" memory access view

14153a3

Introduce an "As CPU (VMA)" access option in the cached access selector to render memory contents as observed by the CPU through the frontend interface.

jdupak force-pushed the feature/sv32-vm-tlb-ptw-cleanup branch from a6cbf71 to bc32933 Compare October 19, 2025 16:13

Basic Virtual Memory Implementation Fixes & Improvements #165

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