📦 piel nix integration

daquintero · Jun 21, 2024 · 717ecea · 717ecea
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diff --git a/.bumpversion.cfg b/.bumpversion.cfg
diff --git a/.github/workflows/create_release.yaml b/.github/workflows/create_release.yaml
@@ -17,36 +17,6 @@ jobs:
         with:
           python-version: 3.x
 
-      - name: Install dependencies
-        run: |
-          python -m pip install --upgrade pip
-          pip install bump2version bumpversion # Install bump2version if not already installed
-
-      - name: Bump version
-        env:
-            GITHUB_USERNAME: daquintero
-            GITHUB_EMAIL: [email protected]
-            GITHUB_TOKEN: ${{ secrets.GITHUB_TOKEN }}
-        run: |
-          # Use the appropriate bumpversion command for your project
-          git config --local user.email "github-actions[bot]@users.noreply.github.com"
-          git config --local user.name "github-actions[bot]"
-          bump2version patch  # Minor increase
-          export VERSION=$(bumpversion --dry-run --list pyproject.toml | grep '^new_version=' | sed -r 's/^new_version=//')
-          echo "VERSION=$VERSION" >> $GITHUB_ENV
-          git tag -d v$VERSION
-          git tag v$VERSION
-
-      - name: Push changes
-        env:
-          GITHUB_USERNAME: daquintero
-          GITHUB_EMAIL: [email protected]
-          GITHUB_TOKEN: ${{ secrets.GITHUB_TOKEN }}
-        uses: ad-m/github-push-action@master
-        with:
-          github_token: ${{ secrets.GITHUB_TOKEN }}
-          tags: true
-
       - name: Create release
         uses: actions/create-release@v1
         env:
@@ -55,59 +25,6 @@ jobs:
           tag_name: v${{ env.VERSION }}  # Use the incremented version as the tag name
           release_name: ${{ env.VERSION }}  # Customize the release name
           body: |
-            Update PYPI ${{ env.VERSION }}
+            Alpha-Release ${{ env.VERSION }}
           draft: false
           release: true
-
-#name: Create Release
-#
-#on:
-#  push:
-#    branches:
-#      - master
-#
-#permissions:
-#  contents: write
-#
-#jobs:
-#  create_release:
-#    runs-on: ubuntu-latest
-#
-#    steps:
-#      - name: Checkout code
-#        uses: actions/checkout@v2
-#
-#      - name: Set up Python
-#        uses: actions/setup-python@v2
-#        with:
-#          python-version: 3.x
-#
-#      - name: Install dependencies
-#        run: |
-#          python -m pip install --upgrade pip
-#          pip install bumpversion  # Install bumpversion if not already installed
-#
-#      - name: Bump version
-#        env:
-#            GITHUB_USERNAME: daquintero
-#            GITHUB_EMAIL: [email protected]
-#            GITHUB_TOKEN: ${{ secrets.GITHUB_TOKEN }}
-#        run: |
-#          # Use the appropriate bumpversion command for your project
-#          bumpversion patch  # Minor increase
-#
-#      - name: Set version as environment variable
-#        run: |
-#          export VERSION=$(bumpversion --dry-run --list | grep '^new_version=' | sed -r 's/^new_version=//')
-#
-#      - name: Create release
-#        uses: actions/create-release@v1
-#        env:
-#          GITHUB_TOKEN: ${{ secrets.GITHUB_TOKEN }}
-#        with:
-#          tag_name: v${{ env.VERSION }}  # Use the incremented version as the tag name
-#          release_name: Release ${{ env.VERSION }}  # Customize the release name
-#          body: |
-#            Update PYPI v${{ env.VERSION }}
-#          draft: false
-#          prerelease: false
diff --git a/README.md b/README.md
@@ -52,10 +52,6 @@ Some existing microservice dependency integrations are:
     Description Library in Python
 - [GDSFactory](https://github.com/gdsfactory/gdsfactory) - An open
     source platform for end to-end photonic chip design and validation
-- [OpenLane v1](https://github.com/The-OpenROAD-Project/OpenLane) - an
-    automated RTL to GDSII flow based on several components including
-    OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for
-    design exploration and optimization
 - [Openlane v2](https://github.com/efabless/openlane2) - The next generation of OpenLane, rewritten from scratch in Python with a modular architecture
 - [sax](https://github.com/flaport/sax) - S-parameter based frequency
     domain circuit simulations and optimizations using JAX.

diff --git a/docs/_static/resources/fsic_2024_presentation.odp b/docs/_static/resources/fsic_2024_presentation.odp
diff --git a/docs/_static/resources/fsic_2024_presentation.pdf b/docs/_static/resources/fsic_2024_presentation.pdf
diff --git a/docs/examples/07_full_flow_demo_electronic_photonic/07_full_flow_demo_electronic_photonic.py b/docs/examples/07_full_flow_demo_electronic_photonic/07_full_flow_demo_electronic_photonic.py
@@ -104,10 +104,6 @@ def create_switch_fabric():
 chain_3_mode_lattice_circuit = create_switch_fabric()
 chain_3_mode_lattice_circuit
 
-from gdsfactory.export import to_svg
-
-to_svg(chain_3_mode_lattice_circuit)
-
 # ## 2. Extracting our optical-to-electronic control logic truth table
 
 
@@ -330,19 +326,21 @@ def create_switch_fabric():
 
 # Now, we could technically also use this simulation to model our optical signal transmission too.
 
-simple_ideal_o4_mzi_2x2_plots = piel.visual.plot_simple_multi_row(
-    data=mzi2x2_simple_simulation_data_lines,
-    x_axis_column_name="t",
-    row_list=[
-        "phase_0",
-        "output_amplitude_array_1_abs",
-        "output_amplitude_array_1_phase_deg",
-    ],
-    y_label=["e1 Phase", "o4 Amplitude", "o4 Phase"],
-)
-simple_ideal_o4_mzi_2x2_plots.savefig(
-    "../_static/img/examples/03a_sax_active_cosimulation/simple_ideal_o4_mzi_2x2_plots.PNG"
-)
+# +
+# # Current work in progress move this out of here.
+# simple_ideal_o4_mzi_2x2_plots = piel.visual.plot_simple_multi_row(
+#     data=mzi2x2_simple_simulation_data_lines,
+#     x_axis_column_name="t",
+#     row_list=[
+#         "phase_0",
+#         "output_amplitude_array_1_abs",
+#         "output_amplitude_array_1_phase_deg",
+#     ],
+#     y_label=["e1 Phase", "o4 Amplitude", "o4 Phase"],
+# )
+# simple_ideal_o4_mzi_2x2_plots.savefig(
+#     "../_static/img/examples/03a_sax_active_cosimulation/simple_ideal_o4_mzi_2x2_plots.PNG"
+# )
 
 # +
 # # Current work in progress move this out of here.
@@ -521,11 +519,17 @@ def create_switch_fabric():
 
 # ## 3b. Digital Chip Implementation
 
+component = piel.flows.get_latest_digital_run_component(
+    module=full_flow_demo,
+)
+component.plot()
+
 component = piel.flows.layout_truth_table(
     truth_table=truth_table,
     module=full_flow_demo,
 )
 
+print("Truth Table Layout")
 component
 
 # ### 4a.

diff --git a/.../examples/07_full_flow_demo_electronic_photonic/full_flow_demo/full_flow_demo/config.json b/.../examples/07_full_flow_demo_electronic_photonic/full_flow_demo/full_flow_demo/config.json
@@ -24,7 +24,7 @@
     },
     "DESIGN_NAME": "top",
     "VERILOG_FILES": "dir::src/*.v",
-    "CLOCK_PORT": "clk",
+    "CLOCK_PORT": "None",
     "CLOCK_PERIOD": 100,
     "RUN_CTS": "false",
     "DIE_AREA": [

diff --git a/...ic/full_flow_demo/full_flow_demo/runs/RUN_2024-06-20_14-47-46/01-yosys-synthesis/COMMANDS b/...ic/full_flow_demo/full_flow_demo/runs/RUN_2024-06-20_14-47-46/01-yosys-synthesis/COMMANDS
@@ -0,0 +1 @@
+yosys -c /nix/store/9jb8wsk32ny2yy5ghcaq3y7mbmmavi2c-python3.11-openlane/lib/python3.11/site-packages/openlane/scripts/yosys/synthesize.tcl
diff --git a/...c/full_flow_demo/full_flow_demo/runs/RUN_2024-06-20_14-47-46/01-yosys-synthesis/_deps.tcl b/...c/full_flow_demo/full_flow_demo/runs/RUN_2024-06-20_14-47-46/01-yosys-synthesis/_deps.tcl
@@ -0,0 +1,11 @@
+set ::_synlig_defines [list]
+verilog_defines -DPDK_sky130A
+lappend ::_synlig_defines +define+PDK_sky130A
+verilog_defines "-DSCL_sky130_fd_sc_hd\""
+lappend ::_synlig_defines "+define+SCL_sky130_fd_sc_hd\""
+verilog_defines -D__openlane__
+lappend ::_synlig_defines +define+__openlane__
+verilog_defines -D__pnr__
+lappend ::_synlig_defines +define+__pnr__
+read_liberty -lib -ignore_miss_dir -setattr blackbox /home/daquintero/.volare/volare/sky130/versions/bdc9412b3e468c102d01b7cf6337be06ec6e9c9a/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__tt_025C_1v80.lib
+set ::env(SYNTH_LIBS) /home/daquintero/phd/piel/docs/examples/07_full_flow_demo_electronic_photonic/full_flow_demo/full_flow_demo/runs/RUN_2024-06-20_14-47-46/tmp/b84aacab8bfd403cbcfe235e5126e1a1.lib
diff --git a/...ic/full_flow_demo/full_flow_demo/runs/RUN_2024-06-20_14-47-46/01-yosys-synthesis/_env.tcl b/...ic/full_flow_demo/full_flow_demo/runs/RUN_2024-06-20_14-47-46/01-yosys-synthesis/_env.tcl
@@ -0,0 +1,86 @@
+set ::env(_DEPS_SCRIPT) /home/daquintero/phd/piel/docs/examples/07_full_flow_demo_electronic_photonic/full_flow_demo/full_flow_demo/runs/RUN_2024-06-20_14-47-46/01-yosys-synthesis/_deps.tcl
+set ::env(STEP_ID) Yosys.Synthesis
+set ::env(TECH_LEF) /home/daquintero/.volare/volare/sky130/versions/bdc9412b3e468c102d01b7cf6337be06ec6e9c9a/sky130A/libs.ref/sky130_fd_sc_hd/techlef/sky130_fd_sc_hd__nom.tlef
+set ::env(MACRO_LEFS) ""
+set ::env(STD_CELL_LIBRARY) sky130_fd_sc_hd
+set ::env(VDD_PIN) VPWR
+set ::env(VDD_PIN_VOLTAGE) 1.80
+set ::env(GND_PIN) VGND
+set ::env(TECH_LEFS) "\"nom_*\" /home/daquintero/.volare/volare/sky130/versions/bdc9412b3e468c102d01b7cf6337be06ec6e9c9a/sky130A/libs.ref/sky130_fd_sc_hd/techlef/sky130_fd_sc_hd__nom.tlef \"min_*\" /home/daquintero/.volare/volare/sky130/versions/bdc9412b3e468c102d01b7cf6337be06ec6e9c9a/sky130A/libs.ref/sky130_fd_sc_hd/techlef/sky130_fd_sc_hd__min.tlef \"max_*\" /home/daquintero/.volare/volare/sky130/versions/bdc9412b3e468c102d01b7cf6337be06ec6e9c9a/sky130A/libs.ref/sky130_fd_sc_hd/techlef/sky130_fd_sc_hd__max.tlef"
+set ::env(GPIO_PADS_LEF) "/home/daquintero/.volare/volare/sky130/versions/bdc9412b3e468c102d01b7cf6337be06ec6e9c9a/sky130A/libs.ref/sky130_fd_io/lef/sky130_fd_io.lef /home/daquintero/.volare/volare/sky130/versions/bdc9412b3e468c102d01b7cf6337be06ec6e9c9a/sky130A/libs.ref/sky130_fd_io/lef/sky130_ef_io.lef"
+set ::env(GPIO_PADS_LEF_CORE_SIDE) "/home/daquintero/.volare/volare/sky130/versions/bdc9412b3e468c102d01b7cf6337be06ec6e9c9a/sky130A/libs.tech/openlane/custom_cells/lef/sky130_fd_io_core.lef /home/daquintero/.volare/volare/sky130/versions/bdc9412b3e468c102d01b7cf6337be06ec6e9c9a/sky130A/libs.tech/openlane/custom_cells/lef/sky130_ef_io_core.lef"
+set ::env(GPIO_PADS_VERILOG) /home/daquintero/.volare/volare/sky130/versions/bdc9412b3e468c102d01b7cf6337be06ec6e9c9a/sky130A/libs.ref/sky130_fd_io/verilog/sky130_ef_io.v
+set ::env(GPIO_PAD_CELLS) "\"sky130_fd_io*\" \"sky130_ef_io*\""
+set ::env(PRIMARY_GDSII_STREAMOUT_TOOL) magic
+set ::env(DATA_WIRE_RC_LAYER) met2
+set ::env(CLOCK_WIRE_RC_LAYER) met5
+set ::env(DEFAULT_CORNER) nom_tt_025C_1v80
+set ::env(STA_CORNERS) "nom_tt_025C_1v80 nom_ss_100C_1v60 nom_ff_n40C_1v95 min_tt_025C_1v80 min_ss_100C_1v60 min_ff_n40C_1v95 max_tt_025C_1v80 max_ss_100C_1v60 max_ff_n40C_1v95"
+set ::env(FP_TRACKS_INFO) /home/daquintero/.volare/volare/sky130/versions/bdc9412b3e468c102d01b7cf6337be06ec6e9c9a/sky130A/libs.tech/openlane/sky130_fd_sc_hd/tracks.info
+set ::env(FP_TAPCELL_DIST) 13
+set ::env(FP_IO_HLAYER) met3
+set ::env(FP_IO_VLAYER) met2
+set ::env(RT_MIN_LAYER) met1
+set ::env(RT_MAX_LAYER) met5
+set ::env(SCL_GROUND_PINS) "VGND VNB"
+set ::env(SCL_POWER_PINS) "VPWR VPB"
+set ::env(TRISTATE_CELLS) "\"sky130_fd_sc_hd__ebuf*\""
+set ::env(FILL_CELL) "\"sky130_fd_sc_hd__fill*\""
+set ::env(DECAP_CELL) "sky130_ef_sc_hd__decap_12 sky130_fd_sc_hd__decap_8 sky130_fd_sc_hd__decap_6 sky130_fd_sc_hd__decap_4 sky130_fd_sc_hd__decap_3"
+set ::env(LIB) "\"*_tt_025C_1v80\" /home/daquintero/.volare/volare/sky130/versions/bdc9412b3e468c102d01b7cf6337be06ec6e9c9a/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__tt_025C_1v80.lib \"*_ss_100C_1v60\" /home/daquintero/.volare/volare/sky130/versions/bdc9412b3e468c102d01b7cf6337be06ec6e9c9a/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ss_100C_1v60.lib \"*_ff_n40C_1v95\" /home/daquintero/.volare/volare/sky130/versions/bdc9412b3e468c102d01b7cf6337be06ec6e9c9a/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ff_n40C_1v95.lib"
+set ::env(CELL_LEFS) "/home/daquintero/.volare/volare/sky130/versions/bdc9412b3e468c102d01b7cf6337be06ec6e9c9a/sky130A/libs.ref/sky130_fd_sc_hd/lef/sky130_ef_sc_hd.lef /home/daquintero/.volare/volare/sky130/versions/bdc9412b3e468c102d01b7cf6337be06ec6e9c9a/sky130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef"
+set ::env(CELL_GDS) /home/daquintero/.volare/volare/sky130/versions/bdc9412b3e468c102d01b7cf6337be06ec6e9c9a/sky130A/libs.ref/sky130_fd_sc_hd/gds/sky130_fd_sc_hd.gds
+set ::env(CELL_VERILOG_MODELS) "/home/daquintero/.volare/volare/sky130/versions/bdc9412b3e468c102d01b7cf6337be06ec6e9c9a/sky130A/libs.ref/sky130_fd_sc_hd/verilog/primitives.v /home/daquintero/.volare/volare/sky130/versions/bdc9412b3e468c102d01b7cf6337be06ec6e9c9a/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v"
+set ::env(CELL_BB_VERILOG_MODELS) "/home/daquintero/.volare/volare/sky130/versions/bdc9412b3e468c102d01b7cf6337be06ec6e9c9a/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd__blackbox.v /home/daquintero/.volare/volare/sky130/versions/bdc9412b3e468c102d01b7cf6337be06ec6e9c9a/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd__blackbox_pp.v"
+set ::env(CELL_SPICE_MODELS) "/home/daquintero/.volare/volare/sky130/versions/bdc9412b3e468c102d01b7cf6337be06ec6e9c9a/sky130A/libs.ref/sky130_fd_sc_hd/spice/sky130_ef_sc_hd__decap_12.spice /home/daquintero/.volare/volare/sky130/versions/bdc9412b3e468c102d01b7cf6337be06ec6e9c9a/sky130A/libs.ref/sky130_fd_sc_hd/spice/sky130_ef_sc_hd__fill_12.spice /home/daquintero/.volare/volare/sky130/versions/bdc9412b3e468c102d01b7cf6337be06ec6e9c9a/sky130A/libs.ref/sky130_fd_sc_hd/spice/sky130_ef_sc_hd__fill_4.spice /home/daquintero/.volare/volare/sky130/versions/bdc9412b3e468c102d01b7cf6337be06ec6e9c9a/sky130A/libs.ref/sky130_fd_sc_hd/spice/sky130_ef_sc_hd__fill_8.spice /home/daquintero/.volare/volare/sky130/versions/bdc9412b3e468c102d01b7cf6337be06ec6e9c9a/sky130A/libs.ref/sky130_fd_sc_hd/spice/sky130_fd_sc_hd.spice"
+set ::env(SYNTH_EXCLUDED_CELL_FILE) /home/daquintero/.volare/volare/sky130/versions/bdc9412b3e468c102d01b7cf6337be06ec6e9c9a/sky130A/libs.tech/openlane/sky130_fd_sc_hd/no_synth.cells
+set ::env(PNR_EXCLUDED_CELL_FILE) /home/daquintero/.volare/volare/sky130/versions/bdc9412b3e468c102d01b7cf6337be06ec6e9c9a/sky130A/libs.tech/openlane/sky130_fd_sc_hd/drc_exclude.cells
+set ::env(OUTPUT_CAP_LOAD) 33.442
+set ::env(MAX_FANOUT_CONSTRAINT) 6
+set ::env(MAX_TRANSITION_CONSTRAINT) 0.75
+set ::env(MAX_CAPACITANCE_CONSTRAINT) 0.2
+set ::env(CLOCK_UNCERTAINTY_CONSTRAINT) 0.25
+set ::env(CLOCK_TRANSITION_CONSTRAINT) 0.1499999999999999944488848768742172978818416595458984375
+set ::env(TIME_DERATING_CONSTRAINT) 5
+set ::env(IO_DELAY_CONSTRAINT) 20
+set ::env(SYNTH_DRIVING_CELL) sky130_fd_sc_hd__inv_2/Y
+set ::env(SYNTH_TIEHI_CELL) sky130_fd_sc_hd__conb_1/HI
+set ::env(SYNTH_TIELO_CELL) sky130_fd_sc_hd__conb_1/LO
+set ::env(SYNTH_BUFFER_CELL) sky130_fd_sc_hd__buf_2/A/X
+set ::env(WELLTAP_CELL) sky130_fd_sc_hd__tapvpwrvgnd_1
+set ::env(ENDCAP_CELL) sky130_fd_sc_hd__decap_3
+set ::env(PLACE_SITE) unithd
+set ::env(CELL_PAD_EXCLUDE) "\"sky130_fd_sc_hd__tap*\" \"sky130_fd_sc_hd__decap*\" \"sky130_ef_sc_hd__decap*\" \"sky130_fd_sc_hd__fill*\""
+set ::env(DIODE_CELL) sky130_fd_sc_hd__diode_2/DIODE
+set ::env(DESIGN_NAME) top
+set ::env(CLOCK_PERIOD) 15
+set ::env(CLOCK_PORT) None
+set ::env(DIE_AREA) "0 0 50 50"
+set ::env(FALLBACK_SDC_FILE) /nix/store/9jb8wsk32ny2yy5ghcaq3y7mbmmavi2c-python3.11-openlane/lib/python3.11/site-packages/openlane/scripts/base.sdc
+set ::env(SYNTH_LATCH_MAP) /home/daquintero/.volare/volare/sky130/versions/bdc9412b3e468c102d01b7cf6337be06ec6e9c9a/sky130A/libs.tech/openlane/sky130_fd_sc_hd/latch_map.v
+set ::env(SYNTH_TRISTATE_MAP) /home/daquintero/.volare/volare/sky130/versions/bdc9412b3e468c102d01b7cf6337be06ec6e9c9a/sky130A/libs.tech/openlane/sky130_fd_sc_hd/tribuff_map.v
+set ::env(SYNTH_CSA_MAP) /home/daquintero/.volare/volare/sky130/versions/bdc9412b3e468c102d01b7cf6337be06ec6e9c9a/sky130A/libs.tech/openlane/sky130_fd_sc_hd/csa_map.v
+set ::env(SYNTH_RCA_MAP) /home/daquintero/.volare/volare/sky130/versions/bdc9412b3e468c102d01b7cf6337be06ec6e9c9a/sky130A/libs.tech/openlane/sky130_fd_sc_hd/rca_map.v
+set ::env(SYNTH_FA_MAP) /home/daquintero/.volare/volare/sky130/versions/bdc9412b3e468c102d01b7cf6337be06ec6e9c9a/sky130A/libs.tech/openlane/sky130_fd_sc_hd/fa_map.v
+set ::env(SYNTH_MUX_MAP) /home/daquintero/.volare/volare/sky130/versions/bdc9412b3e468c102d01b7cf6337be06ec6e9c9a/sky130A/libs.tech/openlane/sky130_fd_sc_hd/mux2_map.v
+set ::env(SYNTH_MUX4_MAP) /home/daquintero/.volare/volare/sky130/versions/bdc9412b3e468c102d01b7cf6337be06ec6e9c9a/sky130A/libs.tech/openlane/sky130_fd_sc_hd/mux4_map.v
+set ::env(USE_LIGHTER) 0
+set ::env(SYNTH_CHECKS_ALLOW_TRISTATE) 1
+set ::env(SYNTH_AUTONAME) 0
+set ::env(SYNTH_STRATEGY) "AREA 0"
+set ::env(SYNTH_ABC_BUFFERING) 0
+set ::env(SYNTH_ABC_LEGACY_REFACTOR) 0
+set ::env(SYNTH_ABC_LEGACY_REWRITE) 0
+set ::env(SYNTH_DIRECT_WIRE_BUFFERING) 1
+set ::env(SYNTH_SPLITNETS) 1
+set ::env(SYNTH_SIZING) 0
+set ::env(SYNTH_NO_FLAT) 0
+set ::env(SYNTH_SHARE_RESOURCES) 1
+set ::env(SYNTH_ADDER_TYPE) YOSYS
+set ::env(SYNTH_ELABORATE_ONLY) 0
+set ::env(SYNTH_ELABORATE_FLATTEN) 1
+set ::env(VERILOG_FILES) /home/daquintero/phd/piel/docs/examples/07_full_flow_demo_electronic_photonic/full_flow_demo/full_flow_demo/src/truth_table_module.v
+set ::env(VERILOG_POWER_DEFINE) USE_POWER_PINS
+set ::env(USE_SYNLIG) 0
+set ::env(SYNLIG_DEFER) 0
+set ::env(SAVE_NETLIST) /home/daquintero/phd/piel/docs/examples/07_full_flow_demo_electronic_photonic/full_flow_demo/full_flow_demo/runs/RUN_2024-06-20_14-47-46/01-yosys-synthesis/top.nl.v