SystemVerilog: --initial-zero
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kroening
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tautschnig
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Feb 20, 2025
src/verilog/verilog_initializer.cpp
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| std::optional<exprt> verilog_zero_initializer(const typet &type) | ||
| { | ||
| if(type.id() == ID_signedbv || type.id() == ID_unsignedbv) | ||
| return from_integer(0, type); | ||
| else if(type.id() == ID_bool) | ||
| return false_exprt{}; | ||
| else if(type.id() == ID_array) | ||
| { | ||
| auto &array_type = to_array_type(type); | ||
| auto zero_element_opt = verilog_zero_initializer(array_type.element_type()); | ||
| if(!zero_element_opt.has_value()) | ||
| return {}; | ||
| else | ||
| return array_of_exprt{*zero_element_opt, array_type}; | ||
| } | ||
| else if(type.id() == ID_struct) | ||
| { | ||
| auto &struct_type = to_struct_type(type); | ||
| exprt::operandst member_values; | ||
| for(auto &component : struct_type.components()) | ||
| { | ||
| auto member_value_opt = verilog_zero_initializer(component.type()); | ||
| if(!member_value_opt.has_value()) | ||
| return {}; | ||
| member_values.push_back(*member_value_opt); | ||
| } | ||
| return struct_exprt{std::move(member_values), struct_type}; | ||
| } | ||
| else | ||
| return {}; | ||
| } |
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It would seem safe to just use zero_initializer from CBMC's code base?
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Do we actually need to make CBMC's zero_initializer easier to extend?
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Yes, it's either that or a copy.
The SystemVerilog standard specifies that variables are to be zero initialized before simulation begins. Some synthesis tools generate logic to achieve this, whereas others do not. This adds the option --initial-zero to match the synthesis semantics when appropriate.
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tautschnig
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We also need extensibility for the solvers, the SMT-LIB converter, and the simplifier. |
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The SystemVerilog standard specifies that variables are to be zero initialized before simulation begins. Some synthesis tools generate logic to achieve this, whereas others do not.
This adds the option
--initial-zeroto match the synthesis semantics when appropriate.