Snippets

vscode-client/package.json

@@ -39,13 +39,29 @@
 			{
 				"language": "vhdl",
 				"scopeName": "source.vhdl",
-				"path": "./syntaxes.vhdl.tmLanguage.json"
+				"path": "./syntaxes/syntaxes.vhdl.tmLanguage.json"
 			}
 		],
 		"snippets": [
 			{
 				"language": "vhdl",
-				"path": "./snippets.vhdl.json"
+				"path": "./snippets/snippets.vhdl.declaration.json"
+			},
+			{
+				"language": "vhdl",
+				"path": "./snippets/snippets.vhdl.generate.json"
+			},
+			{
+				"language": "vhdl",
+				"path": "./snippets/snippets.vhdl.interface.json"
+			},
+			{
+				"language": "vhdl",
+				"path": "./snippets/snippets.vhdl.library.json"
+			},
+			{
+				"language": "vhdl",
+				"path": "./snippets/snippets.vhdl.logic.json"
 			}
 		],
 		"commands": [

vscode-client/snippets/snippets.vhdl.declaration.json

@@ -0,0 +1,127 @@
+{
+	// TODO: open VSC enhancement to allow for user selections ($x) within or (${1||}) selection
+	// TODO: open VSC bug about or selection for doing nothing still requires the editor insert a space or character
+	// TODO: figure out how to column align with snippets such that when new lines are made for things like when/else
+	//       or with select, cursor for next line is aligned with <=
+	// TODO: all types from ieee fixed/floating point packages
+	"Alias": {
+		"prefix": "alias",
+		"body": [
+			"alias ${1:alias_name} : ${2:alias_type} is ${3:object_name};",
+			"$0"
+		],
+		"description": "alias declaration"
+	},
+	// ? are signal/variable/constant all valid for external names
+	"Alias External Name 2008": {
+		"prefix": "alias_external_name_2008",
+		"body": [
+			"alias ${1:name} is",
+			"\t<< ${2|signal,variable,constant|} ${3:path.to.signal.name} : ${4:type} >>;",
+			"$0"
+		],
+		"description": "hierarchical signal declaration (vhdl 2008). NOTE: for standard types (SLV, unsighed, signed, etc.), no range needs to be specified"
+	},
+	"Array": {
+		"prefix": "array",
+		"body": [
+			"type ${1:type_name} is array (${2:natural range<>}) of ${3:element_type};",
+			"$0"
+		],
+		"description": "synthesizable attributes (high,low,left,right,range,reverse_range,length,event)"
+	},
+	"Constant": {
+		"prefix": "constant",
+		"body": [
+			"constant ${1:name} : ${2:type} := ${3:default_value};",
+			"$0"
+		],
+		"description": "constant declaration"
+	},
+	"Function": {
+		"prefix": "function",
+		"body": [
+			"function ${1:name} (${2:params}) return ${3:type} is",
+			"begin",
+			"\t$0",
+			"end function;"
+		],
+		"description": "function body declaration"
+	},
+	"Natural Range": {
+		"prefix": "natural_range",
+		"body": [ "natural range<>" ],
+		"description": "natural range declaration"
+	},
+	"Others": {
+		"prefix": ["others"],
+		"body": [ "(others => ${1:<value>})${2| ,;|}$0" ],
+		"description": "others declaration"
+	},
+	"Procedure": {
+		"prefix": "procedure",
+		"body": [
+			"procedure ${1:name} (${2:params}) is",
+			"begin",
+			"\t$0",
+			"end procedure;"
+		],
+		"description": "procedure body declaration"
+	},
+	"Record": {
+		"prefix": "record",
+		"body": [
+			"type ${1:name} is record",
+			"\t${2:signal_name} : ${3:type};",
+			"\t$0",
+			"end record;"
+		],
+		"description": "record declaration"
+	},
+	"Signal": {
+		"prefix": "signal",
+		"body": [
+			"signal ${1:name} : ${2:type} := ${3:default_value};",
+			"$0"
+		],
+		"description": "signal declaration"
+	},
+	"Signed": {
+		"prefix": "signed",
+		"body": [ "signed($1 ${2|downto,to|} $3)${4| := ,;|}$0" ],
+		"description": "signed declaration"
+	},
+	"Standard Logic": {
+		"prefix": ["std_logic", "sl"],
+		"body": [ "std_logic${1| := ,;|}$0" ],
+		"description": "std_logic declaration"
+	},
+	"Standard ULogic": {
+		"prefix": ["std_ulogic", "sul"],
+		"body": [ "std_ulogic${1| := ,;|}$0" ],
+		"description": "std_ulogic declaration"
+	},
+	"Standard Logic Vector": {
+		"prefix": ["std_logic_vector", "slv"],
+		"body": [ "std_logic_vector($1 ${2|downto,to|} $3)${4| := ,;|}$0" ],
+		"description": "std_logic_vector declaration"
+	},
+	"Standard ULogic Vector": {
+		"prefix": ["std_ulogic_vector", "sulv"],
+		"body": [ "std_ulogic_vector($1 ${2|downto,to|} $3)${4| := ,;|}$0" ],
+		"description": "std_ulogic_vector declaration"
+	},
+	"Unsigned": {
+		"prefix": "unsigned",
+		"body": [ "unsigned(${1} ${2|downto,to|} ${3})${4| := ,;|}$0" ],
+		"description": "unsigned declaration"
+	},
+	"Variable": {
+		"prefix": "variable",
+		"body": [
+			"variable ${1:name} : ${2:type} := ${3:default_value};",
+			"$0"
+		],
+		"description": "variable declaration"
+	}
+}

vscode-client/snippets/snippets.vhdl.generate.json

@@ -0,0 +1,47 @@
+{
+	"Generate If": {
+		"prefix": "generate_if",
+		"body": [
+			"gen_${1:generateName} : if ${2:expression} generate",
+			"\t$0",
+			"end generate;"
+		],
+		"description": "if generate instantiation"
+	},
+	"Generate For": {
+		"prefix": "generate_for",
+		"body": [
+			"gen_loop_${1:generateName} : for ${2:i} in ${3:range} generate",
+			"\t$0",
+			"end generate;"
+		],
+		"description": "for generate loop instantiation (vhdl 2008)"
+	},
+	"Generate Case 2008": {
+		"prefix": "generate_case_2008",
+		"body": [
+			"gen_${1:generateName} : case ${1:select} generate",
+			"\twhen ${2:others} =>",
+			"\t\t${3:null;}",
+			"\t$0",
+			"end generate;"
+		],
+		"description": "case generate instantiation (vhdl 2008)"
+	},
+	"Generate Elsif 2008": {
+		"prefix": "generate_elsif_2008",
+		"body": [
+			"elsif ${1:expression} generate",
+			"\t$0"
+		],
+		"description": "elsif generate instantiation (vhdl 2008)"
+	},
+	"Generate Else 2008": {
+		"prefix": "generate_else_2008",
+		"body": [
+			"\telse generate",
+			"\t\t$0"
+		],
+		"description": "else generate instantiation (vhdl 2008)"
+	}
+}